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Superscalar Instruction Execution in the 21164 Alpha Microprocessor

Published: 01 April 1995 Publication History

Abstract

The 21164 is a new quad-issue superscalar Alpha microprocessor. This new high-performance chip can execute 1.2 billion instructions per second. The part became available in January of 1995 and delivered SPECint92/SPECfp92 performance of 335/500 (estimated), performance unmatched by other commercially available microprocessors. It is implemented in 0.5 micron CMOS and the CPU clock speed is 300 MHz. Instruction execution is controlled by the quad-issue superscalar instruction unit. There are two 64-bit integer execution pipelines and two 64-bit floating-point pipelines. Memory instructions are initiated in the integer pipelines and are completed by the memory and bus interface units that together implement a high-throughput memory subsystem employing a multi-level cache hierarchy.

References

[1]
Alpha Architecture Reference Manual, R. Sites, ed., Digital Press, Burlington, Mass., 1992.
[2]
J. Edmondson, et al., “Internal Organization of the Alpha 21164, a 300-MHz, 64-Bit, Quad-Issue, CMOS RISC Microprocessor,” Digital Technical J., Vol. 7, No. 1, 1995.
[3]
S. Bell, et al., “Circuit Implementation of a 300-MHz, 64-Bit, Second-Generation CMOS Alpha CPU,” Digital Technical J., Vol. 7, No. 1, 1995.
[4]
D.W. Dobberpuhl, et al., “A 200-MHz 64-b Dual-Issue CMOS Microprocessor,” IEEE J. Solid-State Circuits, Vol. 27, No. 11, Nov. 1992, pp. 1555-1564.
[5]
O.L. MacSorley, “High-Speed Arithmetic in Binary Computers,” Proc. IRE, Vol. 49, 1961, pp. 67-91.
[6]
R.L. Sites, “Alpha AXP Architecture,” Special Issue, Digital Technical J., Vol. 4, No. 4, 1992, pp. 19-34.

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        Published In

        cover image IEEE Micro
        IEEE Micro  Volume 15, Issue 2
        April 1995
        83 pages

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        IEEE Computer Society Press

        Washington, DC, United States

        Publication History

        Published: 01 April 1995

        Author Tags

        1. memory
        2. microprocessors
        3. multilevel caches
        4. superscalar chips

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