Article

167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages

Authors:

J. Arjun Prabhu,

Gregory B. ZynerAuthors Info & Claims

ARITH '95: Proceedings of the 12th Symposium on Computer Arithmetic

Page 155

Published: 19 July 1995 Publication History

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Abstract

UltraSPARC's IEEE-754 compliant floating point divide and square root implementation is presented. Three overlapping stages of SRT radix-2 quotient selection logic enable an effective radix-8 calculation at 167 MHz while only a single radix-2 quotient selection logic delay is seen in the critical path. Speculative partial remainder and quotient calculation in the main datapath also improves cycle time. The quotient selection logic is slightly modified to prevent the formation of a negative partial remainder for exact results. This saves latency and hardware as the partial remainder no longer needs to be restored before calculating the sticky bit for rounding.

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Stepchenkov YDiachenko YZakharov VRogdestvenski YMorozov NStepchenkov D(2009)Quasi-delay-insensitive computing deviceProceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-11802-9_32(276-285)Online publication date: 9-Sep-2009
https://dl.acm.org/doi/10.1007/978-3-642-11802-9_32
Guo XSechen C(2005)High Speed Redundant Adder and Divider in Output Prediction LogicProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.38(34-41)Online publication date: 11-May-2005
https://dl.acm.org/doi/10.1109/ISVLSI.2005.38
Oberman SFlynn M(1997)Division Algorithms and ImplementationsIEEE Transactions on Computers10.1109/12.60927446:8(833-854)Online publication date: 1-Aug-1997
https://dl.acm.org/doi/10.1109/12.609274
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ARITH '95: Proceedings of the 12th Symposium on Computer Arithmetic

July 1995

ISBN:0818670894

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IEEE Computer Society

United States

Publication History

Published: 19 July 1995

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Stepchenkov YDiachenko YZakharov VRogdestvenski YMorozov NStepchenkov D(2009)Quasi-delay-insensitive computing deviceProceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-11802-9_32(276-285)Online publication date: 9-Sep-2009
https://dl.acm.org/doi/10.1007/978-3-642-11802-9_32
Guo XSechen C(2005)High Speed Redundant Adder and Divider in Output Prediction LogicProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.38(34-41)Online publication date: 11-May-2005
https://dl.acm.org/doi/10.1109/ISVLSI.2005.38
Oberman SFlynn M(1997)Division Algorithms and ImplementationsIEEE Transactions on Computers10.1109/12.60927446:8(833-854)Online publication date: 1-Aug-1997
https://dl.acm.org/doi/10.1109/12.609274
Tirumalai PGreenley DBeylin BSubramanian K(1996)UltraSPARCProceedings of the 41st IEEE International Computer Conference10.5555/792769.793654Online publication date: 25-Feb-1996
https://dl.acm.org/doi/10.5555/792769.793654
Tremblay MO'Connor J(1996)UltraSparc IIEEE Micro10.1109/40.49146116:2(42-50)Online publication date: 1-Apr-1996
https://dl.acm.org/doi/10.1109/40.491461

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Radix 2 Division with Over-Redundant Quotient Selection

A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture

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