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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 33
Volume 33, Number 1, January 2014
- Vijaykrishnan Narayanan:
Editorial. 1 - Yu Cao
, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze:
Cross-Layer Modeling and Simulation of Circuit Reliability. 8-23 - Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li:
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. 24-35 - Woojoo Lee, Yanzhi Wang, Donghwa Shin, Naehyuck Chang, Massoud Pedram:
Optimizing the Power Delivery Network in a Smartphone Platform. 36-49 - Muhammad Shafique
Adaptive Energy Management for Dynamically Reconfigurable Processors. 50-63 - Yehua Su, Wenjing Rao:
An Integrated Framework Toward Defect-Tolerant Logic Implementation Onto Nanocrossbars. 64-75 - Chip-Hong Chang
A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection. 76-89 - Bing Shi, Ankur Srivastava
Optimized Micro-Channel Design for Stacked 3-D-ICs. 90-100 - Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
Algorithms for Maze Routing With Exact Matching Constraints. 101-112 - En-Jui Chang
Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip Systems. 113-126 - Yi-Hua Li, Wei-Cheng Lien
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing. 127-138 - Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang:
A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification. 139-152 - Hratch Mangassarian, Bao Le, Andreas G. Veneris:
Debugging RTL Using Structural Dominance. 153-166 - Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". 167
Volume 33, Number 2, February 2014
- Bo Liu, Dixian Zhao, Patrick Reynaert
GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm. 169-182 - Yi-Ling Hsieh, Tsung-Yi Ho
Biochip Synthesis and Dynamic Error Recovery for Sample Preparation Using Digital Microfluidics. 183-196 - Georgios D. Dimou, Peter A. Beerel, Andrew Lines:
Performance-Driven Clustering of Asynchronous Circuits. 197-209 - Qin Tang, Javier Rodríguez, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver. 210-223 - Yuan-Kai Ho, Hsu-Chieh Lee, Webber Lee, Yao-Wen Chang
Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs. 224-236 - Kedar Karmarkar, Spyros Tragoudas:
On-Chip Codeword Generation to Cope With Crosstalk. 237-250 - Andrea Calimera
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. 251-264 - Andrea Pellegrini, Valeria Bertacco:
Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation. 265-278 - Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty
Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning. 279-290 - Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs. 291-304 - Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
Sequential Equivalence Checking for Clock-Gated Circuits. 305-317 - Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Considering Crosstalk Effects in Statistical Timing Analysis. 318-322 - Irith Pomeranz:
Unknown Output Values of Faulty Circuits and Output Response Compaction. 323-327
Volume 33, Number 3, March 2014
- Keni Qiu, Mengying Zhao, Qing'an Li, Chenchen Fu, Chun Jason Xue
Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems. 329-342 - Liang Shi, Keni Qiu, Mengying Zhao, Chun Jason Xue
Error Model Guided Joint Performance and Endurance Optimization for Flash Memory. 343-355 - Daniel T. Grissom, Philip Brisk
Fast Online Synthesis of Digital Microfluidic Biochips. 356-369 - Elias Vansteenkiste, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network. 370-383 - Jian Yao, Zuochang Ye, Yan Wang:
Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions. 384-396 - Shao-Yun Fang, Yao-Wen Chang
A Novel Layout Decomposition Algorithm for Triple Patterning Lithography. 397-408 - Jordi Cortadella
A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing. 409-422 - Deokjin Joo, Taewhan Kim:
A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems. 423-436 - Mahdi Nikdast, Jiang Xu
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip. 437-450 - Qi Guo, Tianshi Chen, Yunji Chen
Pre-Silicon Bug Forecast. 451-463 - Brandon Noia, Krishnendu Chakrabarty
Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs. 464-475 - Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. 476-488
Volume 33, Number 4, April 2014
- Cheng-Kok Koh, Chin Ngai Sze:
Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design. 493-494 - Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly:
Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure. 495-506 - Yu-Guang Chen, Hui Geng, Kuan-Yu Lai, Yiyu Shi, Shih-Chieh Chang:
Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment. 507-518 - Tao Wang, Chun Zhang, Jinjun Xiong
On the Deployment of On-Chip Noise Sensors. 519-531 - Logan M. Rakai, Amin Farshidi, David T. Westwick
Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem. 532-545 - Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. 546-557 - Yu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho:
PushPull: Short-Path Padding for Timing Error Resilient Circuits. 558-570 - Kan Wang
Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs. 571-584 - Yang Song, Hao Yu
Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations. 585-598 - Karthick Nagaraj Parashar, Daniel Ménard, Olivier Sentieys:
Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations. 599-612 - Wen-Hao Liu, Yih-Lang Li:
Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing. 613-626 - Kun Ma, Kaijie Wu:
Error Detection and Recovery for ECC: A New Approach Against Side-Channel Attacks. 627-637 - Irith Pomeranz:
Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States. 638-642 - Alexander Finder, André Sülflow, Görschwin Fey
Latency Analysis for Sequential Circuits. 643-647
Volume 33, Number 5, May 2014
- Yingjie Lao, Keshab K. Parhi
Statistical Analysis of MUX-Based Physical Unclonable Functions. 649-662 - Haris Javaid, Muhammad Shafique
Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications. 663-676 - Hussam Amrouch
RESI: Register-Embedded Self-Immunity for Reliability Enhancement. 677-690 - Mohamed Mounir Mahmoud
Design Framework to Overcome Aging Degradation of the 16 nm VLSI Technology Circuits. 691-703 - Fabian Oboril, Mehdi Baradaran Tahoori:
Aging-Aware Design of Microprocessor Instruction Pipelines. 704-716 - S. Ramprasath
Statistical Criticality Computation Using the Circuit Delay. 717-727 - Zheng Zhang
Calculation of Generalized Polynomial-Chaos Basis Functions and Gauss Quadrature Rules in Hierarchical Uncertainty Quantification. 728-740 - Wai-Kei Mak, Chris Chu:
E-Beam Lithography Character and Stencil Co-Optimization. 741-751 - Mohammad H. Foroozannejad, Matin Hashemi
Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms. 752-762 - Cody Hao Yu, Chiao-Ling Lung, Yi-Lun Ho, Ruei-Siang Hsu, Ding-Ming Kwai, Shih-Chieh Chang:
Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization. 763-773 - Sergej Deutsch, Krishnendu Chakrabarty
Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels. 774-785 - Changwook Lee, Wooheon Kang, Donkoo Cho, Sungho Kang:
A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories. 786-797 - Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi, Wei Zhao:
Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects. 798-810
Volume 33, Number 6, June 2014
- Rasit Onur Topaloglu
Guest Editorial Special Section on Optical Interconnects. 813 - Christopher Condrat, Priyank Kalla, Steve Blair:
Crossing-Aware Channel Routing for Integrated Optics. 814-825 - Cheng Li, Mark Browning, Paul V. Gratz
LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip. 826-838 - Hao Zheng, Yingying Zhang:
Local State Space Analysis Leads to Better Partial Order Reduction. 839-852 - Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters. 853-866 - Hans Georg Brachtendorf, Robert C. Melville, Peter Feldmann, Siegmar Lampe, Rainer Laur:
Homotopy Method for Finding the Steady States of Oscillators. 867-878 - Po-Hsun Wu, Mark Po-Hung Lin
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement. 879-892 - Wim Schoenmaker
Computation of Self-Induced Magnetic Field Effects Including the Lorentz Force for Fast-Transient Phenomena in Integrated-Circuit Devices. 893-902 - Yan Luo, Krishnendu Chakrabarty
Biochemistry Synthesis on a Cyberphysical Digital Microfluidics Platform Under Completion-Time Uncertainties in Fluidic Operations. 903-916 - Yanzhi Wang, Xue Lin, Younghyun Kim
Architecture and Control Algorithms for Combating Partial Shading in Photovoltaic Systems. 917-930 - Ivan Ukhov, Petru Eles, Zebo Peng:
Probabilistic Analysis of Power and Temperature Under Process Variation for Electronic System Design. 931-944 - Jayanand Asok Kumar, Seyed Nematollah Ahmadyan, Shobha Vasudevan:
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. 945-958
Volume 33, Number 7, July 2014
- Chenjie Gu, Manzil Zaheer
Multiple-Population Moment Estimation: Exploiting Interpopulation Correlation for Efficient Moment Estimation in Analog/Mixed-Signal Validation. 961-974 - Matthew Morrison, Nagarajan Ranganathan:
Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications. 975-988 - Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). 989-1002 - Graeme Gange, Benjamin Horsfall, Lee Naish, Harald Søndergaard
Four-Valued Reasoning and Cyclic Circuits. 1003-1016 - Bardia Bandali, Emad Gad
Accelerated Harmonic-Balance Analysis Using a Graphical Processing Unit Platform. 1017-1030 - Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang:
Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC. 1031-1042 - Rong Ye, Qiang Xu
Learning-Based Power Management for Multicore Processors via Idle Period Manipulation. 1043-1055 - Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
A Variability-Aware Adaptive Test Flow for Test Quality Improvement. 1056-1066 - Mukesh Agrawal, Michael Richter, Krishnendu Chakrabarty
Test-Delivery Optimization in Manycore SOCs. 1067-1080 - Min Li, Azadeh Davoodi:
A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug. 1081-1094 - Irith Pomeranz:
Selection of Functional Test Sequences With Overlaps. 1095-1099 - Ying Liu, Weizheng Yuan, Honglong Chang
A Global Maximum Error Controller-Based Method for Linearization Point Selection in Trajectory Piecewise-Linear Model Order Reduction. 1100-1104 - Siavash Bayat Sarmadi, Mehran Mozaffari Kermani
Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm. 1105-1109 - Jaeil Lee, Dongkun Shin:
Adaptive Paired Page Prebackup Scheme for MLC NAND Flash Memory. 1110-1114
Volume 33, Number 8, August 2014
- Seobin Jung, Jiho Lee, Jaeha Kim:
Variability-Aware, Discrete Optimization for Analog Circuits. 1117-1130 - Debasis Mitra, Sudip Roy, Sukanta Bhattacharjee, Krishnendu Chakrabarty
On-Chip Sample Preparation for Multiple Targets Using Digital Microfluidics. 1131-1144 - Arvind Sridhar, Mohamed M. Sabry, David Atienza:
A Semi-Analytical Thermal Modeling Framework for Liquid-Cooled ICs. 1145-1158 - Ashish Kumar Singh, Ku He, Constantine Caramanis
Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning. 1159-1167 - Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta
SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology. 1168-1179 - Kunal Banerjee, Chandan Karfa
Verification of Code Motion Techniques Using Value Propagation. 1180-1193 - Karim Kanoun, Nicholas Mastronarde
Online Energy-Efficient Task-Graph Scheduling for Multicore Platforms. 1194-1207 - Sahar Foroutan, Abbas Sheibanyrad, Frédéric Pétrot:
Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCs. 1208-1218 - Joon-Sung Yang, Jinkyu Lee, Nur A. Touba:
Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression. 1219-1230 - Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas
Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. 1231-1244 - Irith Pomeranz:
Simultaneous Generation of Functional and Low-Power Non-Functional Broadside Tests. 1245-1257 - Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng:
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. 1258-1268 - Reinier Gonzalez-Echevarria, Rafael Castro-López
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors. 1269-1273
Volume 33, Number 9, September 2014
- Yongfu Li, Zhe Zhang, Dingjuan Chua, Yong Lian
Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods. 1277-1287 - Jason Oberg, Sarah Meiklejohn, Timothy Sherwood
Leveraging Gate-Level Properties to Identify Hardware Timing Channels. 1288-1301 - Sheng-Han Yeh, Jia-Wen Chang, Tsung-Wei Huang, Shang-Tsung Yu, Tsung-Yi Ho
Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips. 1302-1315 - Shih-Ying Sean Liu, Chung-Hung Chang, Hung-Ming Chen, Tsung-Yi Ho
ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips. 1316-1327 - Zohaib Mahmood, Stefano Grivet-Talocia
Efficient Localization Methods for Passivity Enforcement of Linear Dynamical Models. 1328-1341 - Cinzia Bernardeschi
ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs. 1342-1355 - Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. 1356-1369 - Daniel E. Holcomb, Sanjit A. Seshia:
Compositional Performance Verification of Network-on-Chip Designs. 1370-1383 - Daehyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs. 1384-1395 - Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja Fast:
Cell-Aware Test. 1396-1409 - Ran Wang, Krishnendu Chakrabarty
Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs. 1410-1423 - Jian Yao, Zuochang Ye, Yan Wang:
Scalable Compact Modeling for On-Chip Passive Elements with Correlated Parameter Extraction and Adaptive Boundary Compression. 1424-1428 - Irith Pomeranz:
Functional Broadside Tests for Multistep Defect Diagnosis. 1429-1433
Volume 33, Number 10, October 2014
- Seobin Jung, Jiho Lee, Jaeha Kim:
Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits. 1437-1449 - Duo Liu
Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems. 1450-1462 - Kai Hu, Feiqiao Yu
Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration. 1463-1475 - Matthew Amy, Dmitri Maslov
Polynomial-Time T-Depth Optimization of Clifford+T Circuits Via Matroid Partitioning. 1476-1489 - Zao Liu, Sahana Swarup, Sheldon X.-D. Tan, Hai-Bao Chen, Hai Wang:
Compact Lateral Thermal Resistance Model of TSVs for Fast Finite-Difference Based Thermal Analysis of 3-D Stacked ICs. 1490-1502 - Vladimir Todorov, Daniel Mueller-Gritschneder
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies. 1503-1516 - Subhendu Roy
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. 1517-1530 - Anurag Umbarkar, Varun Subramanian, Alex Doboli:
Linear Programming-Based Optimization for Robust Data Modeling in a Distributed Sensing Platform. 1531-1544 - Da Cheng
Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy. 1545-1558 - Wing Chiu Tam, R. D. (Shawn) Blanton:
Design-for-Manufacturability Assessment for Integrated Circuits Using RADAR. 1559-1572 - David Lin, Ted Hong, Yanjing Li, Eswaran S, Sharad Kumar, Farzan Fallah, Nagib Hakim, Donald S. Gardner
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection. 1573-1590 - Kai-Chiang Wu, Ing-Chao Lin
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs. 1591-1595
Volume 33, Number 11, November 2014
- Semeen Rehman, Florian Kriebel, Muhammad Shafique
Reliability-Driven Software Transformations for Unreliable Hardware. 1597-1610 - Hassan Eldib, Chao Wang:
An SMT Based Method for Optimizing Arithmetic Computations in Embedded Software Code. 1611-1622 - Yi Wang
A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems. 1623-1631 - Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie:
Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems. 1632-1643 - Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. 1644-1656 - Daniel T. Grissom, Jeffrey McDaniel, Philip Brisk
A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip. 1657-1670 - Wan-Yu Wen, Jin-Cheng Li, Sheng-Yuan Lin, Jing-Yi Chen, Shih-Chieh Chang:
A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection. 1671-1680 - Jai-Ming Lin
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint. 1681-1692 - Hsien-Kai Hsin, En-Jui Chang
Ant Colony Optimization-Based Fault-Aware Routing in Mesh-Based Network-on-Chip Systems. 1693-1705 - Wooyoung Jang:
Error-Correcting Code Aware Memory Subsystem. 1706-1717 - Yaoyao Ye, Zhehui Wang
System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip. 1718-1731 - Paul Wettin, Ryan Gary Kim
Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing. 1732-1745 - Ioannis Voyiatzis:
Aliasing Reduction in Accumulator-Based Response Verification. 1746-1750 - Lechang Liu, Ramesh K. Pokharel:
Post-Layout Simulation Time Reduction for Phase-Locked Loop Frequency Synthesizer Using System Identification Techniques. 1751-1755
Volume 33, Number 12, December 2014
- Shreyas Sen, Vishwanath Natarajan, Shyam Kumar Devarakond, Abhijit Chatterjee:
Process-Variation Tolerant Channel-Adaptive Virtually Zero-Margin Low-Power Wireless Receiver Systems. 1764-1777 - Kan Xiao, Domenic Forte
A Novel Built-In Self-Authentication Technique to Prevent Inserting Hardware Trojans. 1778-1791 - Abdullah Nazma Nowroz, Kangqiao Hu, Farinaz Koushanfar
Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps. 1792-1805 - Da-Wei Chang, Ing-Chao Lin, Yu-Shiang Chien, Ching-Lun Lin, Alvin W. Y. Su, Chung-Ping Young:
CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management. 1806-1817 - Robert Wille
Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures. 1818-1831 - Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow
High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. 1832-1845 - Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang:
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking. 1846-1858 - Weiwei Chen, Xu Han, Che-Wei Chang, Guantao Liu, Rainer Dömer:
Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models. 1859-1872 - Jiwoo Pak, Sung Kyu Lim
Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs. 1873-1885 - Jan Malburg, Alexander Finder, Görschwin Fey
A Simulation-Based Approach for Automated Feature Localization. 1886-1899 - Yarui Peng
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. 1900-1913 - Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. 1914-1927 - Chih-Hung Liu
Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction. 1928-1941 - Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang
Nonuniform Multilevel Analog Routing With Matching Constraints. 1942-1954 - Irith Pomeranz:
Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests. 1955-1964 - Joseph Lenox, Spyros Tragoudas:
Adapting an Implicit Path Delay Grading Method for Parallel Architectures. 1965-1976 - Haralampos-G. D. Stratigopoulos, Stephen Sunter:
Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics. 1977-1990 - Georgios Theodorou, Nektarios Kranitis
Software-Based Self-Test for Small Caches in Microprocessors. 1991-2004 - Jaeyong Chung
3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations. 2005-2009 - Irith Pomeranz:
Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests. 2010-2014 - Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal:
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs. 2015-2019 - Chih-Sheng Hou, Jin-Fu Li, Ting-Jun Fu:
A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs. 2020-2024 - Pallab Dasgupta, Mandayam K. Srivas, Rajdeep Mukherjee:
Formal Hardware/Software Co-Verification of Embedded Power Controllers. 2025-2029
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