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Rafael Castro-López
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2020 – today
- 2023
- [c61]Javier Martín-Martínez, Javier Diaz-Fortuny
, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability. IRPS 2023: 1-9 - [c60]Victor M. van Santen, Jose M. Gata-Romero, Juan Núñez
Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. IRPS 2023: 1-6 - [c59]Eros Camacho-Ruiz, F. J. Rubio-Barbero
Design considerations for a CMOS 65-nm RTN-based PUF. SMACD 2023: 1-4 - [c58]Francisco V. Fernández, Elisenda Roca, Pablo Saraza-Canflanca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López
Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices. SMACD 2023: 1-4 - [c57]Jose M. Gata-Romero, Elisenda Roca, Juan Núñez
Reliability evaluation of IC Ring Oscillator PUFs. SMACD 2023: 1-4 - [c56]Jose M. Gata-Romero, Andrés Santana-Andreo, Elisenda Roca, Rafael Castro-López
A Test Module for Aging Characterization of Digital Circuits. SMACD 2023: 1-4 - [c55]F. J. Rubio-Barbero
A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF. SMACD 2023: 1-4 - [c54]Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Rafael Castro-López
A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array. SMACD 2023: 1-4 - 2022
- [j24]Andrés Santana-Andreo
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs. Integr. 85: 1-9 (2022) - [j23]Pablo Saraza-Canflanca
On the Impact of the Biasing History on the Characterization of Random Telegraph Noise. IEEE Trans. Instrum. Meas. 71: 1-10 (2022) - [c53]Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Andrés Santana-Andreo
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies. IRPS 2022: 3-1 - [c52]Eros Camacho-Ruiz, Rafael Castro-López
A novel Physical Unclonable Function using RTN. ISCAS 2022: 160-164 - [c51]Eros Camacho-Ruiz, Rafael Castro-López
High-level design of a novel PUF based on RTN. SMACD 2022: 1-4 - [c50]Eros Camacho-Ruiz, Andrés Santana-Andreo
On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF. SMACD 2022: 1-4 - [c49]Fábio Passos, Nuno C. Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López
Machine Learning Approaches for Transformer Modeling. SMACD 2022: 1-4 - [c48]Andrés Santana-Andreo
Characterization and analysis of BTI and HCI effects in CMOS current mirrors. SMACD 2022: 1-4 - [c47]Andrés Santana-Andreo
Impact of BTI and HCI on the reliability of a Majority Voter. SMACD 2022: 1-4 - [c46]Pablo Saraza-Canflanca, Javier Martín-Martínez, Elisenda Roca, Rafael Castro-López
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation. SMACD 2022: 1-4 - 2021
- [j22]António Canelas
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access 9: 124152-124164 (2021) - 2020
- [j21]Fábio Passos
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. IEEE Access 8: 51601-51609 (2020) - [j20]Pablo Saraza-Canflanca, Javier Diaz-Fortuny
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level. Integr. 72: 13-20 (2020) - [j19]Fábio Passos
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 560-571 (2020) - [j18]Fábio Passos
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4375-4384 (2020) - [j17]Javier Diaz-Fortuny
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits. IEEE Trans. Instrum. Meas. 69(3): 853-864 (2020) - [c45]Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Piedad Brox
Improving the reliability of SRAM-based PUFs in the presence of aging. DTIS 2020: 1-6
2010 – 2019
- 2019
- [j16]Javier Diaz-Fortuny
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI. IEEE J. Solid State Circuits 54(2): 476-488 (2019) - [j15]Fábio Passos
A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits. Soft Comput. 23(13): 4911-4925 (2019) - [j14]Ricardo Martins
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 989-1002 (2019) - [c44]Antonio Toro-Frías, Pablo Saraza-Canflanca
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator. DATE 2019: 78-83 - [c43]Pablo Saraza-Canflanca
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors. DATE 2019: 150-155 - [c42]G. Pedreira, Javier Martín-Martínez, Javier Diaz-Fortuny
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices. IRPS 2019: 1-5 - [c41]Fábio Passos, Elisenda Roca
Synthesis of mm-Wave circuits using-EM-simulated passive structure libraries. SMACD 2019: 57-60 - [c40]Pablo Saraza-Canflanca
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level. SMACD 2019: 197-200 - [c39]Juan Núñez
Experimental Characterization of Time-Dependent Variability in Ring Oscillators. SMACD 2019: 229-232 - [c38]Pablo Martín-Lloret, Juan Núñez
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. SMACD 2019: 241-244 - 2018
- [j13]Fábio Passos
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. Integr. 63: 351-361 (2018) - [j12]Fábio Passos
A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2386-2394 (2018) - [c37]Javier Diaz-Fortuny
CMOS Characterization and Compact Modelling for Circuit Reliability Simulation. IOLTS 2018: 139-142 - [c36]Victor M. van Santen
Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. IRPS 2018: 6-1 - [c35]Enrique Barajas
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology. PATMOS 2018: 82-87 - [c34]Fábio Passos
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. SMACD 2018: 1-164 - [c33]Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López
Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs. SMACD 2018: 1-9 - [c32]Pablo Saraza-Canflanca
Automated Massive RTN Characterization Using a Transistor Array Chip. SMACD 2018: 29-32 - [c31]Javier Diaz-Fortuny
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation. SMACD 2018: 53-56 - [c30]Pablo Saraza-Canflanca
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. SMACD 2018: 73-76 - 2017
- [j11]Fábio Passos
Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling. Appl. Soft Comput. 60: 495-507 (2017) - [j10]Fábio Passos
An inductor modeling and optimization toolbox for RF circuit design. Integr. 58: 463-472 (2017) - [j9]Reinier Gonzalez-Echevarria, Elisenda Roca
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 15-26 (2017) - [c29]Fábio Passos
An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective. CEC 2017: 734-740 - [c28]Pablo Martín-Lloret, Antonio Toro-Frías, Javier Martín-Martínez, Rafael Castro-López
A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs. ISCAS 2017: 1-4 - [c27]Javier Diaz-Fortuny
TARS: A toolbox for statistical reliability modeling of CMOS devices. SMACD 2017: 1-4 - [c26]Javier Diaz-Fortuny
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging. SMACD 2017: 1-4 - [c25]Nuno C. Lourenço
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. SMACD 2017: 1-4 - [c24]Pablo Martín-Lloret, Antonio Toro-Frías, Rafael Castro-López
CASE: A reliability simulation tool for analog ICs. SMACD 2017: 1-4 - [c23]Ricardo Martins
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. SMACD 2017: 1-4 - [c22]Fábio Passos
Systematic design of a voltage controlled oscillator using a layout-aware approach. SMACD 2017: 1-4 - [c21]Antonio Toro-Frías, Pablo Martín-Lloret, Rafael Castro-López
Including a stochastic model of aging in a reliability simulation flow. SMACD 2017: 1-4 - 2016
- [j8]Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López
Reliability simulation for analog ICs: Goals, solutions, and challenges. Integr. 55: 341-348 (2016) - [c20]Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Accurate synthesis of integrated RF passive components using surrogate models. DATE 2016: 397-402 - [c19]Manuel Velasco-Jimenez, Rafael Castro-López
Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms. ISCAS 2016: 1438 - [c18]Manuel Velasco-Jimenez, Rafael Castro-López
High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms. ISCAS 2016: 1494-1497 - [c17]Fábio Passos
SIDe-O: A toolbox for surrogate inductor design and optimization. SMACD 2016: 1-4 - [c16]Fábio Passos
Frequency-dependent parameterized macromodeling of integrated inductors. SMACD 2016: 1-4 - 2015
- [c15]Fábio Passos
Physical vs. surrogate models of passive RF devices. ISCAS 2015: 117-120 - [c14]Manuel Velasco-Jimenez, Rafael Castro-López
Design space exploration using hierarchical composition of performance models. ISCAS 2015: 1941-1944 - 2014
- [j7]Reinier Gonzalez-Echevarria, Rafael Castro-López
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1269-1273 (2014) - [c13]Manuel Velasco-Jimenez, Rafael Castro-López
Implementation issues in the hierarchical composition of performance models of analog circuits. DATE 2014: 1-6 - 2011
- [c12]Antonio Toro-Frías, Rafael Castro-López
Layout-aware Pareto fronts of electronic circuits. ECCTD 2011: 345-348 - 2010
- [j6]Alonso Morgado
A 0.13 µm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications. Microelectron. J. 41(5): 277-290 (2010) - [c11]Francisco V. Fernández
Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors. IEEE Congress on Evolutionary Computation 2010: 1-8
2000 – 2009
- 2009
- [j5]Rafael Castro-López
AMS/RF-CMOS circuit design for wireless transceivers. Integr. 42(1): 1-2 (2009) - [j4]José M. de la Rosa, Rafael Castro-López
Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey. Microelectron. J. 40(1): 156-176 (2009) - [j3]Bo Liu, Francisco V. Fernández
A memetic approach to the automatic design of high-performance analog integrated circuits. ACM Trans. Design Autom. Electr. Syst. 14(3): 42:1-42:24 (2009) - [c10]Helmut Gräb, Florin Balasa, Rafael Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser:
Analog layout synthesis - Recent advances in topological approaches. DATE 2009: 274-279 - [c9]Elisenda Roca
Hierarchical synthesis based on pareto-optimal fronts. ECCTD 2009: 755-758 - [c8]Elisenda Roca
Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview. ICECS 2009: 251-254 - 2008
- [j2]Alonso Morgado
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK. Integr. 41(2): 269-280 (2008) - [j1]Rafael Castro-López
An Integrated Layout-Synthesis Approach for Analog ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1179-1189 (2008) - 2006
- [c7]Jesús Ruiz-Amaya, Manuel Delgado-Restituto
A 12-bit CMOS Current Steering D/A Converter for Embedded Systems. APCCAS 2006: 1671-1674 - 2003
- [c6]Rafael Castro-López, Francisco V. Fernández, Fernando Medeiro, Ángel Rodríguez-Vázquez:
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages. DATE 2003: 10168-10175 - [c5]Gustavo Liñán Cembrano
A 1000FPS@128×128 vision processor with 8-bit digitized I/O. ESSCIRC 2003: 61-64 - [c4]Rafael Castro-López, José M. de la Rosa, R. Romay, Rocío del Río, Fernando Medeiro, Francisco V. Fernández:
Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey. FDL 2003: 121-133 - [c3]Rafael Castro-López, Francisco V. Fernández, Fernando Medeiro, Ángel Rodríguez-Vázquez:
Accurate VHDL-based simulation of Sigma-Delta modulators. ISCAS (4) 2003: 632-635 - 2001
- [c2]Rafael Castro-López
Retargeting of mixed-signal blocks for SoCs. DATE 2001: 772-775
1990 – 1999
- 1999
- [c1]José E. Franca, Nuno Horta
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design. ICECS 1999: 1679-1683
Coauthor Index
[c61] [c59] [c58] [c57] [c56] [c55] [c54] [j24] [j23] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [j22] [j21] [j20] [j19] [j18] [j17] [c45] [j16] [j15] [j14] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [j13] [j12] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j11] [j10] [j9] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [j8] [c20] [c17] [c16] [c15] [c14] [j7] [c13] [c12] [c11] [j5] [j4] [j3] [c10] [c9] [c8] [j2] [j1] [c6] [c4] [c3] [c2] [c1]
Elisenda Roca
aka: Elisenda Roca Moreno
aka: Elisenda Roca Moreno
[c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [j24] [j23] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [j22] [j21] [j20] [j19] [j18] [j17] [c45] [j16] [j15] [j14] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [j13] [j12] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j11] [j10] [j9] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [j8] [c20] [c17] [c16] [c15] [c14] [j7] [c13] [c12] [c11] [j3] [c9] [c8] [j1]
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