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Jiang Xu 0001
須江
Person information
- unicode name: 須江
- affiliation: Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong
- affiliation (PhD 2007): Princeton University, NJ, USA
Other persons with the same name
- Jiang Xu — disambiguation page
- Jiang Xu 0002 — Northwestern University, Department of Electrical Engineering and Computer Science, Evanston, IL, USA
- Jiang Xu 0003
— Huazhong University of Science and Technology, State Engineering Research Center of Manufacturing Equipment Digitization, Wuhan, China
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2020 – today
- 2024
- [j55]Xiao Li
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1726-1739 (2024) - [c65]Xianbin Li
NEOCNN: NTT-Enabled Optical Convolution Neural Network Accelerator. ICS 2024: 352-362 - [c64]Yuxiang Fu, Xuanqi Chen, Jiaxu Zhang, Shixi Chen, Jiang Xu:
Towards Thermally Reliable Photonic Links for Multicore Processors. ISVLSI 2024: 260-265 - [c63]Lin Chen
PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer. SPAA 2024: 359-370 - 2023
- [c62]Lin Chen, Xiao Li, Fan Jiang, Chengeng Li, Jiang Xu:
Smart Knowledge Transfer-based Runtime Power Management. DATE 2023: 1-6 - [c61]Chengeng Li, Fan Jiang, Shixi Chen, Xianbin Li
RONet: Scaling GPU System with Silicon Photonic Chiplet. ICCAD 2023: 1-9 - [c60]Yinyi Liu, Bohan Hu
FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator. ICCAD 2023: 1-9 - [c59]Chengao Shi
Memory Workload Synthesis Using Generative AI. MEMSYS 2023: 7:1-7:7 - 2022
- [j54]Xuanqi Chen, Yuxiang Fu
Improving the thermal reliability of photonic chiplets on multicore processors. Integr. 86: 9-21 (2022) - [j53]Zhifei Wang
HERO: Pbit High-Radix Optical Switch Based on Integrated Silicon Photonics for Data Center. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 908-921 (2022) - [j52]Fan Jiang
Fast and Accurate Statistical Simulation of Shared-Memory Applications on Multicore Systems. IEEE Trans. Parallel Distributed Syst. 33(10): 2455-2469 (2022) - [c58]Yinyi Liu, Jiaqi Liu
PHANES: ReRAM-based photonic accelerator for deep neural networks. DAC 2022: 103-108 - [c57]Yinyi Liu, Jiaxu Zhang, Jun Feng, Shixi Chen, Jiang Xu:
A Reliability Concern on Photonic Neural Networks. DATE 2022: 1059-1064 - [c56]Lin Chen, Xiao Li
Improve the Stability and Robustness of Power Management through Model-free Deep Reinforcement Learning. DATE 2022: 1371-1376 - [c55]Chengeng Li, Fan Jiang, Shixi Chen, Jiaxu Zhang, Yinyi Liu, Yuxiang Fu, Jiang Xu:
Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet. ICCAD 2022: 43:1-43:9 - [c54]Jun Feng, Shixi Chen, Jiaxu Zhang, Yuxiang Fu, Jiang Xu:
Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems. ISVLSI 2022: 122-127 - [c53]Xiao Li, Lin Chen, Shixi Chen, Fan Jiang, Chengeng Li, Jiang Xu:
Power Management for Chiplet-Based Multicore Systems Using Deep Reinforcement Learning. ISVLSI 2022: 164-169 - [c52]Yinyi Liu, Jiaxu Zhang, Jun Feng, Shixi Chen, Jiang Xu:
Reduce Footprints of Multiport Interferometers by Cosine-Sine-Decomposition Unfolding. OFC 2022: 1-3 - 2021
- [j51]Zhehui Wang
Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics Through Multichip Partition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 101-114 (2021) - [j50]Xuanqi Chen
Simultaneously Tolerate Thermal and Process Variations Through Indirect Feedback Tuning for Silicon Photonic Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1409-1422 (2021) - [c51]Jun Feng
Rejuvenate Post-Moore's Law Computing with Photonics-Electronics Hybrid Systems. ICICDT 2021: 1-3 - [c50]Zhongyuan Tian, Lin Chen, Xiao Li
Multi-Core Power Management through Deep Reinforcement Learning. ISCAS 2021: 1-5 - 2020
- [j49]Peng Yang
Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 626-639 (2020) - [j48]Zhifei Wang
A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 640-653 (2020) - [j47]Xuanqi Chen
Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(5): 977-990 (2020) - [j46]Zhehui Wang
CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1820-1833 (2020) - [j45]Zhongyuan Tian
Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1128-1140 (2020) - [j44]Haoran Li
Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1150-1163 (2020) - [c49]Shixi Chen, Jiang Xu, Xuanqi Chen
Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors. DATE 2020: 1628-1633
2010 – 2019
- 2019
- [j43]Luan H. K. Duong
Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 43-56 (2019) - [j42]Zhongyuan Tian
Collaborative Power Management Through Knowledge Sharing Among Multiple Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1203-1215 (2019) - [j41]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c48]Zhifei Wang, Jun Feng
Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters. ICCAD 2019: 1-8 - [c47]Jun Feng
Scalable Low-Power High-Performance Rack-Scale Optical Network. PHOTONICS@SC 2019: 1-6 - 2018
- [j40]Jiang Xu, Yuichi Nakamura, Andrew B. Kahng:
Silicon Photonics for Computing Systems. ACM J. Emerg. Technol. Comput. Syst. 14(2): 20 (2018) - [j39]Haoran Li
Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2076-2086 (2018) - [j38]Weichen Liu
A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems. IEEE Trans. Multi Scale Comput. Syst. 4(2): 113-126 (2018) - [c46]Zhongyuan Tian, Zhe Wang, Haoran Li, Peng Yang, Rafael Kioji Vivas Maeda, Jiang Xu:
Multi-device collaborative management through knowledge sharing. ASP-DAC 2018: 22-27 - [c45]Peng Yang, Zhengbin Pang, Zhifei Wang, Zhehui Wang
RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems. DATE 2018: 1369-1374 - [c44]Haoran Li
Co-manage power delivery and consumption for manycore systems using reinforcement learning. ICCAD 2018: 34 - [c43]Zhongyuan Tian, Haoran Li, Rafael Kioji Vivas Maeda, Jun Feng, Jiang Xu:
Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing. ICCD 2018: 409-412 - [c42]Xuanqi Chen
A Comprehensive Electro-Optical Model for Silicon Photonic Switches. ISVLSI 2018: 76-81 - [e1]Zhonghai Lu, Sriram R. Vangal, Jiang Xu, Paul Bogdan:
Twelfth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, Torino, Italy, October 4-5, 2018. IEEE 2018, ISBN 978-1-5386-4893-3 [contents] - 2017
- [j37]Haoran Li
Energy-Efficient Power Delivery System Paradigms for Many-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 449-462 (2017) - [j36]Krishnendu Chakrabarty
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [c41]Zhe Wang, Zhongyuan Tian, Jiang Xu, Rafael K. V. Maeda, Haoran Li
Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system. ASP-DAC 2017: 684-689 - [c40]Zhehui Wang
MOCA: an Inter/Intra-Chip Optical Network for Memory. DAC 2017: 86:1-86:6 - [c39]Haoran Li, Jiang Xu, Zhe Wang, Peng Yang, Rafael K. V. Maeda, Zhongyuan Tian:
Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators. DATE 2017: 1265-1268 - [c38]Rafael K. V. Maeda, Qiong Cai, Jiang Xu, Zhe Wang, Zhongyuan Tian:
Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance. HPCA 2017: 145-156 - [c37]Kang Yao, Yaoyao Ye, Sudeep Pasricha, Jiang Xu:
Thermal-sensitive design and power optimization for a 3D torus-based optical NoC. ICCAD 2017: 827-834 - 2016
- [j35]Xuan Wang, Jiang Xu, Zhe Wang, Haoran Li, Peng Yang, Luan H. K. Duong, Rafael K. V. Maeda, Zhifei Wang
Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign. ACM J. Emerg. Technol. Comput. Syst. 13(2): 19:1-19:24 (2016) - [j34]Weichen Liu
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1546-1559 (2016) - [j33]Zhehui Wang
Improve Chip Pin Performance Using Optical Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1574-1587 (2016) - [j32]Zhehui Wang
A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2462-2474 (2016) - [j31]Luan H. K. Duong
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2475-2487 (2016) - [j30]Zhe Wang, Xuan Wang, Jiang Xu, Haoran Li, Rafael K. V. Maeda, Zhehui Wang
An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3373-3386 (2016) - [c36]Rafael K. V. Maeda, Peng Yang, Xiaowen Wu, Zhe Wang, Jiang Xu, Zhehui Wang
JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models. AISTECS@HiPEAC 2016: 8:1-8:6 - [c35]Peng Yang, Shigeru Nakamura, Kenichiro Yashiki, Zhehui Wang
Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations. NOCS 2016: 1-8 - 2015
- [j29]Xuan Wang, Jiang Xu
An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1401-1414 (2015) - [j28]Mahdi Nikdast, Jiang Xu, Luan H. K. Duong, Xiaowen Wu, Zhehui Wang
Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 156-169 (2015) - [j27]Xuan Wang, Jiang Xu
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 266-279 (2015) - [j26]Xiaowen Wu, Jiang Xu, Yaoyao Ye, Xuan Wang, Mahdi Nikdast, Zhehui Wang
An Inter/Intra-Chip Optical Network for Manycore Processors. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 678-691 (2015) - [j25]Mahdi Nikdast, Jiang Xu, Luan Huu Kinh Duong
Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2552-2565 (2015) - [c34]Zhehui Wang
Alleviate chip I/O pin constraints for multicore processors through optical interconnects. ASP-DAC 2015: 791-796 - [c33]Zhe Wang, Xuan Wang, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong, Haoran Li, Rafael Kioji Vivas Maeda, Zhifei Wang:
Adaptively tolerate power-gating-induced power/ground noise under process variations. DATE 2015: 483-488 - [c32]Luan H. K. Duong, Mahdi Nikdast, Jiang Xu, Zhehui Wang, Yvain Thonnart, Sébastien Le Beux, Peng Yang, Xiaowen Wu, Zhifei Wang:
Coherent crosstalk noise analyses in ring-based optical interconnects. DATE 2015: 501-506 - [c31]Chuan Tang, Dan Liu, Zuocheng Xing, Peng Yang, Zhe Wang, Jiang Xu:
Memory Access Analysis of Many-core System with Abundant Bandwidth. MCSoC 2015: 187-194 - [c30]Lu Ding, Ning Zheng, Jiang Xu, Ming Xu:
An Improved Content-Based Music Recommending Method with Weighted Tags. MMM (1) 2015: 360-371 - 2014
- [j24]Luan H. K. Duong
A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip. IEEE Des. Test 31(5): 55-65 (2014) - [j23]Weichen Liu
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip. ACM J. Emerg. Technol. Comput. Syst. 10(2): 15:1-15:20 (2014) - [j22]Xiaowen Wu, Jiang Xu, Yaoyao Ye, Zhehui Wang
SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor. ACM J. Emerg. Technol. Comput. Syst. 10(4): 29:1-29:25 (2014) - [j21]Zhehui Wang
Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors. IEEE Trans. Computers 63(6): 1446-1459 (2014) - [j20]Mahdi Nikdast, Jiang Xu
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 437-450 (2014) - [j19]Yaoyao Ye, Zhehui Wang
System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1718-1731 (2014) - [j18]Xiaowen Wu, Yaoyao Ye, Jiang Xu
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1082-1095 (2014) - [c29]Zhe Wang, Weichen Liu
A systematic network-on-chip traffic modeling and generation methodology. APCCAS 2014: 675-678 - [c28]Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang:
Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors. DATE 2014: 1-4 - [c27]Zhe Wang, Weichen Liu
A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs. ISVLSI 2014: 480-485 - [c26]Jiang Xu, Sébastien Le Beux, Yvain Thonnart
Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?". NOCS 2014: 167 - [c25]Mahdi Nikdast, Luan H. K. Duong, Jiang Xu
CLAP: a crosstalk and loss analysis platform for optical interconnects. NOCS 2014: 172-173 - 2013
- [j17]Kai Feng, Yaoyao Ye, Jiang Xu
A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip. Microprocess. Microsystems 37(8-B): 941-952 (2013) - [j16]Yaoyao Ye, Jiang Xu
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 584-596 (2013) - [j15]Weichen Liu
On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip. IEEE Trans. Parallel Distributed Syst. 24(4): 767-777 (2013) - [j14]Yaoyao Ye, Jiang Xu
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 292-305 (2013) - [j13]Yiyuan Xie, Mahdi Nikdast, Jiang Xu
Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1823-1836 (2013) - [c24]Xuan Wang, Jiang Xu
Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories. DATE 2013: 1221-1224 - [c23]Yaoyao Ye, Xiaowen Wu, Jiang Xu
System-level analysis of mesh-based hybrid optical-electronic network-on-chip. ISCAS 2013: 321-324 - [i1]Tomohiro Yoneda, José Flich Cardo, Jiang Xu, Michihiro Koibuchi:
Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). NII Shonan Meet. Rep. 2013 (2013) - 2012
- [j12]Yaoyao Ye, Jiang Xu
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. 8(1): 5:1-5:26 (2012) - 2011
- [j11]Weichen Liu
Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models. IEEE Embed. Syst. Lett. 3(1): 46-49 (2011) - [j10]Xing Wen, Oscar C. Au, Jiang Xu
Novel RD-Optimized VBSME With Matching Highly Data Re-Usable Hardware Architecture. IEEE Trans. Circuits Syst. Video Technol. 21(2): 206-219 (2011) - [j9]Weichen Liu
Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems. IEEE Trans. Parallel Distributed Syst. 22(8): 1382-1389 (2011) - [j8]Yu Wang
Power Gating Aware Task Scheduling in MPSoC. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1801-1812 (2011) - [c22]Xing Wen, Oscar C. Au, Jiang Xu
Sub-pixel downsampling of video with matching highly data re-use hardware architecture. ISCAS 2011: 1495-1499 - [c21]Weichen Liu
A NoC Traffic Suite Based on Real Applications. ISVLSI 2011: 66-71 - [c20]Yaoyao Ye, Jiang Xu
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. ISVLSI 2011: 254-259 - [c19]Weichen Liu
A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC. ISVLSI 2011: 260-265 - 2010
- [j7]Huaxi Gu
A new distributed congestion control mechanism for networks on chip. Telecommun. Syst. 44(3-4): 321-331 (2010) - [c18]Yiyuan Xie, Mahdi Nikdast, Jiang Xu
Crosstalk noise and bit error rate analysis for optical network-on-chip. DAC 2010: 657-660 - [c17]Xing Wen, Oscar C. Au, Jiang Xu
A highly data reusable and standard-compliant motion estimation hardware architecture. ICME 2010: 220-225 - [c16]Mo Kwai Hung, Yaoyao Ye, Xiaowen Wu, Wei Zhang
A Hierarchical Hybrid Optical-Electronic Network-on-Chip. ISVLSI 2010: 327-332 - [c15]Xiaowen Wu, Yaoyao Ye, Wei Zhang
UNION: A unified inter/intra-chip optical network for chip multiprocessors. NANOARCH 2010: 35-40
2000 – 2009
- 2009
- [j6]Weichen Liu
Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow. IEEE Embed. Syst. Lett. 1(3): 69-72 (2009) - [j5]Zonghua Gu
Efficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs. Microprocess. Microsystems 33(5-6): 374-387 (2009) - [j4]Jiang Xu
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs. IEEE Micro 29(3): 20-30 (2009) - [c14]Yaoyao Ye, Lian Duan, Jiang Xu
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). 3DIC 2009: 1-6 - [c13]Yu Wang, Jiang Xu
A case study of on-chip sensor network in multiprocessor system-on-chip. CASES 2009: 241-250 - [c12]Weichen Liu
An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking. CODES+ISSS 2009: 61-70 - [c11]Huaxi Gu, Jiang Xu, Wei Zhang:
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip. DATE 2009: 3-8 - [c10]Xing Wen, Oscar C. Au, Jiang Xu
A Novel Multiple Description Video Coding based on H.264/AVC Video Coding Standard. ISCAS 2009: 1237-1240 - [c9]Huaxi Gu
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip. ISVLSI 2009: 19-24 - [c8]Yan Xu, Weichen Liu
On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise. ISVLSI 2009: 109-114 - 2008
- [c7]Huaxi Gu
A novel optical mesh network-on-chip for gigascale systems-on-chip. APCCAS 2008: 1728-1731 - [c6]Huaxi Gu
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip. CODES+ISSS 2008: 203-208 - 2006
- [j3]Jiang Xu, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar:
A design methodology for application-specific networks-on-chip. ACM Trans. Embed. Comput. Syst. 5(2): 263-280 (2006) - 2005
- [j2]Tiehan Lv, Jiang Xu, Wayne H. Wolf, I. Burak Özer, Jörg Henkel, Srimat T. Chakradhar:
A Methodology for Architectural Design of Multimedia Multiprocessor SoCs. IEEE Des. Test Comput. 22(1): 18-26 (2005) - [c5]Jiang Xu, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar:
H.264 HDTV Decoder Using Application-Specific Networks-On-Chip. ICME 2005: 1508-1511 - [c4]Jiang Xu, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar:
A methodology for design, modeling, and analysis of networks-on-chip. ISCAS (2) 2005: 1778-1781 - 2004
- [c3]Jiang Xu, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv:
A Case Study in Networks-on-Chip Design for Embedded Video. DATE 2004: 770-777 - 2003
- [j1]Yuan Xie, Jiang Xu, Wayne H. Wolf:
Augmenting Platform-Based Design with Synthesis Tools. J. Circuits Syst. Comput. 12(2): 125-142 (2003) - [c2]Jiang Xu, Wayne H. Wolf:
A wave-pipelined on-chip interconnect structure for networks-on-chips. Hot Interconnects 2003: 10-14 - 2002
- [c1]Jiang Xu, Wayne H. Wolf:
Wave pipelining for application-specific networks-on-chips. CASES 2002: 198-201
Coauthor Index
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