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Helmut Reinig
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2010 – 2019
- 2014
- [j2]Vladimir Todorov, Daniel Mueller-Gritschneder
, Helmut Reinig, Ulf Schlichtmann
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1503-1516 (2014) - 2013
- [c14]Vladimir Todorov, Daniel Mueller-Gritschneder
A spectral clustering approach to application-specific network-on-chip synthesis. DATE 2013: 1783-1788 - 2012
- [c13]Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs. CODES+ISSS 2012: 181-186 - [c12]Vladimir Todorov, Daniel Mueller-Gritschneder
Automated construction of a cycle-approximate transaction level model of a memory controller. DATE 2012: 1066-1071 - 2011
- [c11]Hervé Tatenguem
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study. NoCArc@MICRO 2011: 37-42 - 2010
- [c10]Andreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig:
Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. NOCS 2010: 17-24
2000 – 2009
- 2009
- [c9]Andreas Lankes, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig:
NoC topology exploration for mobile multimedia applications. ICECS 2009: 707-710 - 2008
- [c8]Sören Sonntag, Helmut Reinig:
An Efficient Weighted-Round-Robin Algorithm for Multiprocessor Architectures. Annual Simulation Symposium 2008: 193-199
1990 – 1999
- 1999
- [b1]Helmut Reinig:
A scalable architecture for custom computing. Kaiserslautern University of Technology, Germany, 1999, pp. I-VIII, 1-224 - 1998
- [c7]Markus Brandstetter, Torsten Harms, Helmut Reinig, Michael Vanrompay:
Codevelopment of long haul ISDN transceiver and design methodology improves time to market. ICECS 1998: 407-410 - 1996
- [j1]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. 8(6): 429-443 (1996) - [c6]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design 1996: 81-84 - 1995
- [c5]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt:
A Parallelizing Compilation Method for the Map-oriented Machine. ASAP 1995: 129-132 - 1994
- [c4]Reiner W. Hartenstein, Rainer Kress, Helmut Reinig:
A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP 1994: 404-414 - [c3]Reiner W. Hartenstein, Rainer Kress, Helmut Reinig:
A New FPGA Architecture for Word-Oriented Datapaths. FPL 1994: 144-155 - [c2]Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Data-Procedural Languages for FPL-based Machines. FPL 1994: 183-195 - 1992
- [c1]Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL 1992: 211-217
Coauthor Index
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