default search action
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 19
Volume 19, Number 1, January 2000
- Chuanjin Richard Shi, Sheldon X.-D. Tan:
Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams. 1-18 - Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu
:
Efficient design exploration based on module utility selection. 19-29 - Miodrag Potkonjak, Jan M. Rabaey:
Maximally and arbitrarily fast implementation of linear andfeedback linear computations. 30-43 - Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan:
Sibling-substitution-based BDD minimization using don't cares. 44-55 - Steven J. E. Wilton:
Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. 56-68 - Mahbub Hasan, Huan-Hsiang Patrick Shen, David R. Allee, Michael J. Pennell:
A behavioral model of a 1.8-V flash A/D converter based on deviceparameters. 69-82 - Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Equivalent Elmore delay for RLC trees. 83-97 - Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston:
Transient sensitivity computation in controlled explicit piecewiselinear simulation. 98-110 - Indradeep Ghosh
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. 111-128 - Wanli Jiang, Bapiraju Vinnakota:
IC test using the energy consumption ratio. 129-141 - Zheng Rong Yang, Mark Zwolinski
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification. 142-151 - Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang:
TAIR: testability analysis by implication reasoning. 152-160 - H. M. Chen, G. S. Samudra, D. S. H. Chan, Yaacob Ibrahim:
Global optimization for digital MOS circuits performance. 161-164 - Spiridon Nikolaidis
Estimation of signal transition activity in FIR filters implementedby a MAC architecture. 164-169
Volume 19, Number 2, February 2000
- Martin D. F. Wong
Editorial. 173-174 - Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky
Optimal phase conflict removal for layout of dark field alternatingphase shifting masks. 175-187 - Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai:
Timing optimization on routed designs with incremental placementand routing characterization. 188-196 - Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang:
Interconnect thermal modeling for accurate simulation of circuittiming and reliability. 197-205 - Wei Chen, Cheng-Ta Hsieh, Massoud Pedram:
Simultaneous gate sizing and placement. 206-214 - Jason Cong, Jie Fang, Kei-Yong Khoo:
Via design rule consideration in multilayer maze routing algorithms. 215-223 - Kunihiro Fujiyoshi, Hiroshi Murata:
Arbitrary convex and concave rectilinear block packing usingsequence-pair. 224-233 - Sung-Woo Hur, Ashok Jagannathan, John Lillis:
Timing-driven maze routing. 234-241 - Dennis Sylvester, Kurt Keutzer:
A global wiring paradigm for deep submicron design. 242-252 - Ching-Han Tsai, Sung-Mo Kang:
Cell-level placement for improving substrate thermal distribution. 253-266 - Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hypergraph partitioning with fixed vertices [VLSI CAD]. 267-272 - Evangeline F. Y. Young, Martin D. F. Wong
Slicing floorplans with range constraint. 272-278
Volume 19, Number 3, March 2000
- Evguenii I. Goldberg, Luca P. Carloni
Negative thinking in branch-and-bound: the case of unate covering. 281-294 - Hen-Ming Lin, Jing-Yang Jou:
On computing the minimum feedback vertex set of a directed graph bycontraction operations. 295-307 - Ganesh Lakshminarayana, Anand Raghunathan
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. 308-324 - Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung:
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver. 325-338 - Pasquale Cocchini, Massoud Pedram:
Fanout optimization using bipolar LT-trees. 339-349 - Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes:
Performance optimization by interacting netlist transformations andplacement. 350-358 - Gerard A. Allan:
Yield prediction by sampling IC layout. 359-371 - Irith Pomeranz, Sudhakar M. Reddy:
On n-detection test sets and variable n-detection test sets fortransition faults. 372-383 - Rolf Drechsler
Fast exact minimization of BDD's. 384-389 - Kyung Suk Oh:
Accurate transient simulation of transmission lines with the skineffect. 389-396
Volume 19, Number 4, April 2000
- Sheldon X.-D. Tan, Chuanjin Richard Shi:
Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams. 401-412 - Ian O'Connor, Andreas Kaiser
Automated synthesis of current-memory cells. 413-424 - Kenneth L. Shepard, Zhong Tian:
Return-limited inductances: a practical approach to on-chipinductance extraction. 425-436 - Chauchin Su, Yue-Tsang Chen:
Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. 437-445 - Jiang Hu, Sachin S. Sapatnekar
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. 446-458 - Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
A multilevel engine for fast power simulation of realistic inputstreams. 459-472 - Jennifer Y. Dong, Ajoy Opal:
Time-domain thermal noise simulation of switched capacitor circuitsand delta-sigma modulators. 473-481 - Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III:
Integrated parametric timing optimization of digital systems. 482-489 - Jue Wu, Elizabeth M. Rudnick:
Bridge fault diagnosis using stuck-at fault simulation. 489-495
Volume 19, Number 5, May 2000
- Wendy Belluomini, Chris J. Myers
Timed state space exploration using POSETs. 501-520 - Christoph Meinel, Fabio Somenzi, Thorsten Theobald:
Linear sifting of decision diagrams and its application insynthesis. 521-533 - Shantanu Dutt, Wenyong Deng:
Probability-based approaches to VLSI circuit partitioning. 534-549 - Sachin S. Sapatnekar
A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing. 550-559 - Andreas Hössinger, Erasmus Langer, Siegfried Selberherr
Parallelization of a Monte Carlo ion implantation simulator. 560-567 - Sreejit Chakravarty, Sujit T. Zachariah:
STBM: a fast algorithm to simulate IDDQ tests forleakage faults. 568-576 - Kun-Jin Lin, Cheng-Wen Wu
Testing content-addressable memories using functional fault modelsand march-like algorithms. 577-588 - Irith Pomeranz, Sudhakar M. Reddy:
A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. 589-600 - Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti:
Model checking on timed-event structures. 601-611 - Jun Dong Cho
Wiring space and length estimation in two-dimensional arrays. 612-615 - Taewhan Kim, Junhyung Um:
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. 615-624 - Xiaoyu Song, Qian-Yu Tang, Dian Zhou, Yuke Wang:
Wire space estimation and routability analysis. 624-628
Volume 19, Number 6, June 2000
- Edoardo Charbon:
Guest Editorial. 633-634 - Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser:
Clock skew verification in the presence of IR-drop in the powerdistribution network. 635-644 - J. Briaire, K. S. Krisch:
Principles of substrate crosstalk generation in CMOS circuits. 645-653 - Akio Koyama, Makio Uchida, Tatsuhiro Aida, Jun'ya Kudo, Masatoshi Tsuge:
Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme. 654-670 - Makoto Nagata
Measurements and analyses of substrate noise waveform inmixed-signal IC environment. 671-678 - Chandramouli Visweswariah, Ruud A. Haring, Andrew R. Conn:
Noise considerations in circuit optimization. 679-690 - Prashant Saxena, C. L. Liu:
A postprocessing algorithm for crosstalk-driven wire perturbation. 691-702 - Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar
Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search. 703-717
Volume 19, Number 7, July 2000
- Florin Balasa, Koen Lampaert:
Symmetry within the sequence-pair representation in the context ofplacement for analog design. 721-731 - Jui-Ming Chang, Massoud Pedram:
Codex-dp: co-design of communicating systems using dynamicprogramming. 732-744 - Zhaoxuan Shen, Ching-Chuen Jong
Functional area lower bound and upper bound on multicomponentselection for interval scheduling. 745-759 - Fabrizio Ferrandi
Symbolic optimization of interacting controllers based onredundancy identification and removal. 760-772 - Dingming Xie, Leonard Forbes:
Phase noise on a 2-GHz CMOS LC oscillator. 773-778 - Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. 779-788 - Bapiraju Vinnakota, Ramesh Harjani:
DFT for digital detection of analog parametric faults in SC filters. 789-798 - Pavan K. Gunupudi
Simulation of high-speed distributed interconnects using Krylov-space techniques. 799-808 - Subodh Gupta, Farid N. Najm:
Analytical models for RTL power estimation of combinational andsequential circuits. 808-814 - C. A. J. van Eijk:
Sequential equivalence checking based on structural similarities. 814-819 - Hai Zhou, Martin D. F. Wong
Simultaneous routing and buffer insertion with restrictions onbuffer locations. 819-824
Volume 19, Number 8, August 2000
- Tamal Mukherjee
Efficient handling of operating range and manufacturing linevariations in analog cell synthesis. 825-839 - Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
SPFD: A new method to express functional flexibility. 840-849 - Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie:
Distributed-memory parallel routing for field-programmable gatearrays. 850-862 - Indradeep Ghosh
A fast and low-cost testing technique for core-based system-chips. 863-877 - Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Cellular automata-based test pattern generators with phase shifters. 878-893 - Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. 894-906 - Paul Tafertshofer, Andreas Ganz, Kurt Antreich:
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation. 907-927 - Huan-Chih Tsai, Kwang-Ting Cheng
On improving test quality of scan-based BIST. 928-938 - Karsten Strehl, Lothar Thiele:
Interval diagrams for efficient symbolic verification of processnetworks. 939-956 - Ilker Hamzaoglu, Janak H. Patel:
Test set compaction algorithms for combinational circuits. 957-963 - Ming-Bo Lin:
On the design of fast large fan-in CMOS multiplexers. 963-967
Volume 19, Number 9, September 2000
- Luca Benini, Alberto Macii
Architectures and synthesis algorithms for power-efficient businterfaces. 969-980 - Norman Scheinberg, Aleksey Pinkhasov:
A computer simulation model for simulating distortion in FETresistors. 981-989 - Zheng-Yu Yuan, Zheng-Fan Li, Min-Liu Zou:
Computer-aided analysis of on-chip interconnects near semiconductorsubstrate for high-speed VLSI. 990-998 - Iris Hui-Ru Jiang, Yao-Wen Chang
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. 999-1010 - Dirk Stroobandt, Peter Verplaetse, Jan M. Van Campenhout
Generating synthetic benchmark circuits for evaluating CAD tools. 1011-1022 - Koichi Nose, Takayasu Sakurai:
Analysis and future trend of short-circuit power. 1023-1030 - Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
A fast signature computation algorithm for LFSR and MISR. 1031-1040 - Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan:
VERILAT: verification using logic augmentation and transformations. 1041-1051 - Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska:
Star test: the theory and its applications. 1052-1064 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Improving symbolic reachability analysis by means of activityprofiles. 1065-1075 - Susanta Chakrabarti, Sandip Das, Debesh Kumar Das, Bhargab B. Bhattacharya:
Synthesis of symmetric functions for path-delay fault testability. 1076-1081 - Craig M. Files, Marek A. Perkowski:
New multivalued functional decomposition algorithms based on MDDs. 1081-1086 - Irith Pomeranz, Sudhakar M. Reddy:
On synchronizable circuits and their synchronizing sequences. 1086-1092
Volume 19, Number 10, October 2000
- Henrik Hulgaard, Tod Amon:
Symbolic timing analysis of asynchronous systems. 1093-1104 - Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana:
Integrating variable-latency components into high-level synthesis. 1105-1117 - Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky
New approximation algorithms for routing with multiport terminals. 1118-1128 - Ion I. Mandoiu
A new heuristic for rectilinear Steiner trees. 1129-1139 - Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh:
Congestion minimization during placement. 1140-1148 - Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S. 1149-1162 - Krishnendu Chakrabarty
Test scheduling for core-based systems using mixed-integer linearprogramming. 1163-1174 - Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer:
Automated synthesis of phase shifters for built-in self-testapplications. 1175-1188 - Pramodchandran N. Variyam, Abhijit Chatterjee:
Specification-driven test generation for analog circuits. 1189-1201 - Seungjoon Park, Satyaki Das, David L. Dill:
Automatic checking of aggregation abstractions through stateenumeration. 1202-1210 - Yi-Kan Cheng, Sung-Mo Kang:
A temperature-aware simulation environment for reliable ULSI chipdesign. 1211-1220 - Haksu Kim, Dian Zhou:
Efficient implementation of a planar clock routing with thetreatment of obstacles. 1220-1225 - Aiguo Xie, Peter A. Beerel:
Implicit enumeration of strongly connected components and anapplication to formal verification. 1225-1230
Volume 19, Number 11, November 2000
- Robert Kosik, Peter Fleischmann, Bernhard Haindl, Paola Pietra
On the interplay between meshing and discretization inthree-dimensional diffusion simulation. 1233-1240 - Andrea Pacelli, Marco Mastrapasqua, Serge Luryi:
Generation of equivalent circuits from physics-based devicesimulation. 1241-1250 - Shantanu Tarafdar, Miriam Leeser
A data-centric approach to high-level synthesis. 1251-1267 - Jason Cong, Songjie Xu:
Performance-driven technology mapping for heterogeneous FPGAs. 1268-1281 - Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini:
Fast and efficient parametric modeling of contact-to-substratecoupling. 1282-1292 - Dingming Xie, Mengzhang Cheng, Leonard Forbes:
SPICE models for flicker noise in n-MOSFETs from subthreshold tostrong inversion. 1293-1303 - Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Optimal partitioners and end-case placers for standard-cell layout. 1304-1313 - Joachim Pistorius, Edmée Legai, Michel Minoux:
PartGen: a generator of very large circuits to benchmark thepartitioning of FPGAs. 1314-1321 - Min Zhao, Sachin S. Sapatnekar
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. 1322-1336 - Sachio Hayashi, Masaaki Yamada:
EMI-noise analysis under ASIC design environment. 1337-1346 - Mukund Sivaraman, Andrzej J. Strojwas:
Primitive path delay faults: identification and their use in timinganalysis. 1347-1362 - Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
Estimation of power dissipation using a novel power macromodelingtechnique. 1363-1369 - Tong Liu, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi:
Testing and testable designs for one-time programmable FPGAs. 1370-1375 - Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams:
BIST hardware synthesis for RTL data paths based on testcompatibility classes. 1375-1385 - Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". 1386-1388 - Xiaodong Zhang, Wenlei Shan, Kaushik Roy:
Low-power weighted random pattern testing. 1389-1398
Volume 19, Number 12, December 2000
- Raul Camposano, Massoud Pedram:
Electronic design automation at the turn of the century: accomplishments and vision of the future. 1401-1403 - Jochen A. G. Jess:
Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itself. 1404-1427 - Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams:
An industrial view of electronic design automation. 1428-1448 - Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi:
Fundamental CAD algorithms. 1449-1475 - John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan:
EDA in IBM: past, present, and future. 1476-1497 - T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Gregory S. Spirakis, Naveed A. Sherwani, Craig Peterson:
EDA challenges facing future microprocessor design. 1498-1506 - Kazutoshi Wakabayashi, Takumi Okamoto:
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective. 1507-1522 - Kurt Keutzer, A. Richard Newton, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
System-level design: orthogonalization of concerns andplatform-based design. 1523-1543 - Robert W. Dutton, Andrzej J. Strojwas:
Perspectives on technology and technology-driven CAD. 1544-1560 - Kenneth S. Kundert, Henry Chang, Dan Jefferies, Gilles Lamant, Enrico Malavasi, Fred Sendig:
Design of mixed-signal systems-on-a-chip. 1561-1571 - Tamal Mukherjee
Emerging simulation approaches for micromachined devices. 1572-1589
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-18 20:50 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: