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Debesh Kumar Das
Debesh K. Das
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2020 – today
- 2024
- [j31]Joyati Mondal
, Debesh Kumar Das, Bhargab B. Bhattacharya:
Design-for-testability for reversible logic circuits based on bit-swapping. IET Quantum Commun. 5(2): 113-122 (2024) - [j30]Sabyasachee Banerjee
Power-aware partitioning and test time reduction for 3D-SoC. Innov. Syst. Softw. Eng. 20(3): 485-498 (2024) - [j29]Asfak Ali
IRUVD: a new still-image based dataset for automatic vehicle detection. Multim. Tools Appl. 83(3): 6755-6781 (2024) - [c71]Tanusree Kaibartta, Hitarth Arora, Debesh Kumar Das:
Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs. VLSID 2024: 730-735 - 2022
- [j28]Joyati Mondal
A new online testing technique for reversible circuits. IET Quantum Commun. 3(1): 50-59 (2022) - [j27]Joyati Mondal
DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits. J. Circuits Syst. Comput. 31(10): 2250128:1-2250128:24 (2022) - [c70]Subrata Das
Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect. VDAT 2022: 373-386 - [c69]Habibur Rahaman, Santanu Chattopadhyay
Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking. VLSID 2022: 246-251 - [i2]Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya:
Improved Upper Bound on Independent Domination Number for Hypercubes. CoRR abs/2205.06671 (2022) - 2021
- [j26]Tanusree Kaibartta
A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC. IEEE Access 9: 160987-161002 (2021) - [j25]Sabyasachee Banerjee
Fast algorithms for test optimization of core based 3D SoC. Integr. 77: 70-88 (2021) - [j24]Joyati Mondal, Arighna Deb
An Efficient Design for Testability Approach of Reversible Logic Circuits. J. Circuits Syst. Comput. 30(6): 2150094:1-2150094:31 (2021) - [c68]Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das:
Minimization of Switching Activity of Graphene Based Circuits. VLSID 2021: 139-144 - 2020
- [j23]Tanusree Kaibartta
Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs. J. Electron. Test. 36(2): 239-253 (2020) - [j22]Arindam Banerjee
A Novel ALU Circuit based on Reversible Logic. J. Circuits Syst. Comput. 29(11): 2050172:1-2050172:17 (2020) - [j21]Subrata Das
A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects. ACM J. Emerg. Technol. Comput. Syst. 16(3): 31:1-31:28 (2020) - [c67]Tanusree Kaibartta, G. P. Biswas, Debesh K. Das:
Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing. ATS 2020: 1-6 - [c66]Joyati Mondal, Debesh Kumar Das:
An Improved Online Testing Technique For Reversible Circuits. ISDCS 2020: 1-5
2010 – 2019
- 2019
- [j20]Tanusree Kaibartta, Chandan Giri
Approach of genetic algorithm for power-aware testing of 3D IC. IET Comput. Digit. Tech. 13(5): 383-396 (2019) - [j19]Joyati Mondal
Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits. J. Circuits Syst. Comput. 28(12): 1950212:1-1950212:18 (2019) - [c65]Arindam Banerjee, Debesh Kumar Das:
Arithmetic Circuits Using Reversible Logic: A Survey Report. ACSS (1) 2019: 99-110 - [c64]Arighna Deb, Debesh K. Das:
Detailed Fault Model for Physical Quantum Circuits. ATS 2019: 153-158 - [c63]Sayantani Roy, Arighna Deb, Debesh K. Das:
Delay Efficient All Optical Carry Lookahead Adder. VDAT 2019: 236-244 - 2018
- [c62]Subrata Das, Debesh Kumar Das:
Floorplanning in Graphene Nanoribbon (GNR) Based Circuits. ISVLSI 2018: 293-298 - [c61]Tanusree Kaibartta, Debesh Kumar Das:
Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach. VDAT 2018: 310-321 - 2017
- [j18]Arighna Deb, Debesh K. Das:
An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata. Microprocess. Microsystems 53: 157-167 (2017) - [c60]Joyati Mondal, Debesh Kumar Das:
Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing. ATS 2017: 248-253 - [c59]Sabyasachee Banerjee
A placement optimization technique for 3D IC. ISED 2017: 1-5 - [c58]Subrata Das, Debesh Kumar Das:
A technique to construct global routing trees for graphene nanoribbon (GNR). ISQED 2017: 111-118 - 2016
- [j17]Arindam Banerjee
A New Squarer design with reduced area and delay. IET Comput. Digit. Tech. 10(5): 205-214 (2016) - [j16]Arighna Deb, Debesh K. Das, Hafizur Rahaman
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. ACM J. Emerg. Technol. Comput. Syst. 12(4): 34:1-34:29 (2016) - [c57]Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das:
A rule-based approach for minimizing power dissipation of digital circuits. DDECS 2016: 237-242 - [c56]Subrata Das, Soma Das, Adrija Majumder, Parthasarathi Dasgupta, Debesh Kumar Das:
Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees. ACM Great Lakes Symposium on VLSI 2016: 263-268 - [c55]Arindam Banerjee, Debesh Kumar Das:
A new ALU architecture design using reversible logic. ISED 2016: 187-191 - [c54]Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya, Tsutomu Sasao:
On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults. ISMVL 2016: 276-281 - [c53]Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das:
Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. VDAT 2016: 1-6 - [c52]Arindam Banerjee, Debesh Kumar Das:
Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. VLSID 2016: 385-390 - 2015
- [j15]Debesh Kumar Das, Hideo Fujiwara:
One More Class of Sequential Circuits having Combinational Test Generation Complexity. J. Electron. Test. 31(3): 321-327 (2015) - [j14]Arindam Banerjee
The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics. J. Low Power Electron. 11(4): 467-478 (2015) - [c51]Joyati Mondal, Debesh K. Das, Bhargab B. Bhattacharya:
Design-for-testability in reversible logic circuits based on bit-swapping. ATS 2015: 217-222 - [c50]Joyati Mondal, Bappaditya Mondal
Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits. DDECS 2015: 95-98 - [c49]Tanusree Kaibartta, Debesh K. Das:
Testing of 3D IC with minimum power using genetic algorithm. IDT 2015: 112-117 - [c48]Arighna Deb, Robert Wille
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. ISMVL 2015: 14-19 - [c47]Arindam Banerjee, Debesh Kumar Das:
Squarer design with reduced area and delay. VDAT 2015: 1-6 - [c46]Sabyasachee Banerjee
Partitioning-based test time reduction for core-based 3DICs. VDAT 2015: 1-5 - 2014
- [j13]Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay:
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. J. Low Power Electron. 10(3): 443-454 (2014) - [c45]Bappaditya Mondal
Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method. ATS 2014: 68-73 - [c44]Arindam Banerjee, Debesh Kumar Das:
Squaring in reversible logic using iterative structure. EWDTS 2014: 1-4 - [c43]Manjari Pradhan
Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning. EWDTS 2014: 1-4 - [c42]Arighna Deb, Debesh K. Das, Bhargab B. Bhattacharya:
Synthesis of Symmetric Boolean Functions Using a Three-Stage Network. ISED 2014: 182-186 - [c41]Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao:
Inadmissible Class of Boolean Functions under Stuck-at Faults. ISMVL 2014: 237-242 - [c40]Rupali Mitra
On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties. ISVLSI 2014: 202-207 - [c39]Arighna Deb, Debesh Kumar Das:
A regular network of symmetric functions in quantum-dot cellular automata. VDAT 2014: 1-6 - 2013
- [j12]Dipak Kumar Kole, Hafizur Rahaman
Derivation of test set for detecting multiple missing-gate faults in reversible circuits. Comput. Electr. Eng. 39(2): 225-236 (2013) - [c38]Manjari Pradhan
Optimal stacking of SOCs in a 3D-SIC for post-bond testing. 3DIC 2013: 1-5 - [c37]Joyati Mondal, Debesh K. Das, Dipak Kumar Kole, Hafizur Rahaman
A design for testability technique for quantum reversible circuits. EWDTS 2013: 1-4 - [c36]Arighna Deb, Debesh K. Das, Hafizur Rahaman
Reversible synthesis of symmetric boolean functions based on unate decomposition. ACM Great Lakes Symposium on VLSI 2013: 351-352 - [c35]Arindam Banerjee, Debesh Kumar Das:
The Design of Reversible Multiplier Using Ancient Indian Mathematics. ISED 2013: 31-35 - [c34]Arighna Deb, Debesh K. Das, Susmita Sur-Kolay:
Modular Design for Symmetric Functions Using Quantum Quaternary Logic. ISED 2013: 143-147 - [c33]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. RC 2013: 182-195 - [c32]Joyati Mondal, Debesh Kumar Das, Dipak Kumar Kole, Hafizur Rahaman
On Designing Testable Reversible Circuits Using Gate Duplication. VDAT 2013: 322-329 - [i1]Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao:
Inadmissible Class of Boolean Functions under Stuck-at Faults. CoRR abs/1309.3993 (2013) - 2012
- [c31]Papia Manna, Dipak Kumar Kole, Hafizur Rahaman
Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization. ISED 2012: 246-250 - 2011
- [j11]Hafizur Rahaman
Fault diagnosis in reversible circuits under missing-gate fault model. Comput. Electr. Eng. 37(4): 475-485 (2011) - [c30]Dipak Kumar Kole, Hafizur Rahaman
Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits. ISED 2011: 200-205 - [c29]Surajit Kumar Roy, Chandan Giri
Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. ISED 2011: 230-235 - 2010
- [c28]Dipak Kumar Kole, Hafizur Rahaman
Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits. Asian Test Symposium 2010: 33-38
2000 – 2009
- 2009
- [j10]Hafizur Rahaman
Testable design of AND-EXOR logic networks with universal test sets. Comput. Electr. Eng. 35(5): 644-658 (2009) - 2008
- [j9]Hafizur Rahaman
An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell. IEEE Trans. Instrum. Meas. 57(12): 2838-2845 (2008) - [c27]Debesh K. Das:
Key Note Speaker. ICIIS 2008: 1 - [c26]Hafizur Rahaman
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. VLSI Design 2008: 163-168 - 2007
- [c25]Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya:
Optimum Test Set for Bridging Fault Detection in Reversible Circuits. ATS 2007: 125-128 - 2006
- [j8]Hafizur Rahaman
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. J. Electron. Test. 22(2): 125-142 (2006) - 2005
- [j7]Biplab K. Sikdar
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. J. Electron. Test. 21(1): 83-93 (2005) - [c24]Hafizur Rahaman, Debesh K. Das:
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. ASP-DAC 2005: 172-177 - [c23]Biplab K. Sikdar
Synthesis of Testable Finite State Machine Through Decomposition. Asian Test Symposium 2005: 398-403 - [c22]Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das:
Cellular Automata Based Test Structures with Logic Folding. VLSI Design 2005: 71-74 - 2004
- [j6]Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian:
Design & Test Education in Asia. IEEE Des. Test Comput. 21(4): 331-338 (2004) - [j5]Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara:
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electron. Test. 20(3): 315-323 (2004) - [c21]Hafizur Rahaman, Debesh K. Das:
A Simple Delay Testable Synthesis of Symmetric Functions. AACC 2004: 263-270 - [c20]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. ASP-DAC 2004: 224-229 - [c19]Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara:
Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. Asian Test Symposium 2004: 342-347 - [c18]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. VLSI Design 2004: 487-492 - 2003
- [c17]Hafizur Rahaman
Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. Asian Test Symposium 2003: 284-289 - 2002
- [j4]Hafizur Rahaman
BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. J. Comput. Sci. Technol. 17(6): 731-737 (2002) - [c16]Hafizur Rahaman
A New Synthesis of Symmetric Functions. ASP-DAC/VLSI Design 2002: 160-165 - [c15]Samir Roy, Biplab K. Sikdar
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. ASP-DAC/VLSI Design 2002: 671-676 - 2001
- [c14]Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri:
Cellular automata as a built in self test structure. ASP-DAC 2001: 319-324 - [c13]Biplab K. Sikdar
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. Asian Test Symposium 2001: 285- - [c12]Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara:
Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design 2001: 128-133 - [c11]Biplab K. Sikdar
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. VLSI Design 2001: 403- - 2000
- [j3]Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya:
Isomorph-Redundancy in Sequential Circuits. IEEE Trans. Computers 49(9): 992-997 (2000) - [j2]Susanta Chakrabarti, Sandip Das, Debesh Kumar Das, Bhargab B. Bhattacharya:
Synthesis of symmetric functions for path-delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1076-1081 (2000) - [c10]Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara:
Test Generation for Acyclic Sequential Circuits with Hold Registers. ICCAD 2000: 550-556
1990 – 1999
- 1999
- [c9]Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. ASP-DAC 1999: 287- - [c8]Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara:
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium 1999: 263-268 - [c7]Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya:
Synthesis of Symmetric Functions for Path-Delay Fault Testability. VLSI Design 1999: 512-517 - 1998
- [c6]Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya:
Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. ASP-DAC 1998: 469-474 - [c5]Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya:
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. VLSI Design 1998: 205- - 1997
- [c4]Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya:
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. VLSI Design 1997: 303-309 - 1996
- [c3]Debesh Kumar Das, Bhargab B. Bhattacharya:
Does retiming affect redundancy in sequential circuits? VLSI Design 1996: 260-263 - [c2]Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya:
Isomorph-redundancy in sequential circuits. VTS 1996: 463-469 - 1995
- [c1]Debesh K. Das, Bhargab B. Bhattacharya:
Testable design of non-scan sequential circuits using extra logic. Asian Test Symposium 1995: 176- - 1993
- [j1]Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya:
Logical redundancies in irredundant combinational circuits. J. Electron. Test. 4(2): 125-130 (1993)
Coauthor Index
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last updated on 2024-10-07 22:11 CEST by the dblp team
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