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Wolfgang Günther 0001
Person information
- affiliation: OneSpin Solutions GmbH, Munich, Germany
- affiliation (PhD 2001): University of Freiburg, Germany
Other persons with the same name
- Wolfgang Günther — disambiguation page
- Wolfgang Günther 0002 — Technische Hochschule Magdeburg, Germany
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2000 – 2009
- 2006
- [j14]Thomas Eschbach, Wolfgang Günther, Bernd Becker
:
Orthogonal Hypergraph Drawing for Improved Visibility. J. Graph Algorithms Appl. 10(2): 141-157 (2006) - 2005
- [j13]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Combining ordered best-first search with branch and bound for exact BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1515-1529 (2005) - [c42]Thomas Eschbach, Wolfgang Günther, Bernd Becker
Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. VLSI Design 2005: 433-438 - 2004
- [c41]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
Minimization of the expected path length in BDDs based on local changes. ASP-DAC 2004: 865-870 - [c40]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
Combining ordered best-first search with branch and bound for exact BDD minimization. ASP-DAC 2004: 875-878 - [c39]Thomas Eschbach, Wolfgang Günther, Bernd Becker
Orthogonal hypergraph routing for improved visibility. ACM Great Lakes Symposium on VLSI 2004: 385-388 - [c38]Wolfgang Günther, Stefan Höreth:
Some Common Synthesis-Simulation-Mismatches. MBMV 2004: 127-136 - [c37]Rolf Drechsler, Wolfgang Günther, Burkhard Stubert:
Efficient (Non-)Reachability Analysis of Counterexamples. MBMV 2004: 250-259 - 2003
- [j12]Ilia Polian, Wolfgang Günther, Bernd Becker
Pattern-based verification of connections to intellectual property cores. Integr. 35(1): 25-44 (2003) - [j11]Rolf Drechsler
Recursive bi-partitioning of netlists for large number of partitions. J. Syst. Archit. 49(12-15): 521-528 (2003) - [j10]Wolfgang Günther, Rolf Drechsler
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. IEEE Trans. Computers 52(9): 1196-1209 (2003) - [j9]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
An improved branch and bound algorithm for exact BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12): 1657-1663 (2003) - [c36]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
Combination of Lower Bounds in Exact BDD Minimization. DATE 2003: 10758-10763 - [c35]Ilia Polian, Wolfgang Günther, Bernd Becker:
The Case for 2-POF. MBMV 2003: 164-173 - [c34]Thomas Eschbach, Wolfgang Günther, Bernd Becker:
Cross Reduction for Orthogonal Circuit Visualization. VLSI 2003: 107-113 - 2002
- [j8]Wolfgang Günther, Rolf Drechsler
Minimization of free BDDs. Integr. 32(1-2): 41-59 (2002) - [j7]Rolf Drechsler
Minimization of Word-Level Decision Diagrams. Integr. 33(1-2): 39-70 (2002) - [j6]Mitchell A. Thornton
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs. VLSI Design 14(1): 53-64 (2002) - [c33]Rolf Drechsler
Recursive Bi-Partitioning of Netlists for Large Number of Partitions. DSD 2002: 38-44 - [c32]Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
Crossing Reduction by Windows Optimization. GD 2002: 285-294 - 2001
- [b1]Wolfgang Günther:
Minimierung von Entscheidungsdiagrammen und Anwendungen im Schaltkreisentwurf. University of Freiburg, Freiburg im Breisgau, Germany, 2001, pp. 1-186 - [j5]Rolf Drechsler
History-based dynamic BDD minimization. Integr. 31(1): 51-63 (2001) - [j4]Rolf Drechsler
Using lower bounds during dynamic BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 51-57 (2001) - [c31]Wolfgang Günther, Andreas Hett, Bernd Becker:
Application of linearly transformed BDDs in sequential verification. ASP-DAC 2001: 91-96 - [c30]Ilia Polian, Wolfgang Günther, Bernd Becker:
Efficient Pattern-Based Verification of Connections to IP Cores . Asian Test Symposium 2001: 443-448 - [c29]Bernd Becker
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. DSD 2001: 54-61 - [c28]Rolf Drechsler
Level Assignment for Displaying Combinational Logic. DSD 2001: 148-151 - [c27]Frank Schmiedle, Wolfgang Günther, Rolf Drechsler:
Selection of Efficient Re-Ordering Heuristics for MDD Construction. ISMVL 2001: 299-304 - [c26]Ilia Polian, Wolfgang Günther, Bernd Becker:
Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. MBMV (1) 2001: 111-120 - [c25]Wolfgang Günther, Rolf Drechsler:
Implementation of Read- k-times BDDs on Top of Standard BDD Packages. VLSI Design 2001: 173-178 - [c24]Wolfgang Günther, Rolf Drechsler:
Performance Driven Optimization for MUX based FPGAs. VLSI Design 2001: 311-316 - 2000
- [j3]Wolfgang Günther, Rolf Drechsler
On the computational power of linearly transformed BDDs. Inf. Process. Lett. 75(3): 119-125 (2000) - [j2]Wolfgang Günther, Rolf Drechsler
ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. J. Syst. Archit. 46(14): 1321-1334 (2000) - [j1]Rolf Drechsler
Fast exact minimization of BDD's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 384-389 (2000) - [c23]Wolfgang Günther, Nicole Drechsler, Rolf Drechsler
Verification of Designs Containing Black Boxes. EUROMICRO 2000: 1100-1105 - [c22]Wolfgang Günther, Rolf Drechsler:
ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. EUROMICRO 2000: 1130-1137 - [c21]Rolf Drechsler
Testability of Circuits Derived from Lattice Diagrams. EUROMICRO 2000: 1188-1192 - [c20]Wolfgang Günther, Robby Schönfeld, Bernd Becker
k-Layer Straightline Crossing Minimization by Speeding Up Sifting. GD 2000: 253-258 - [c19]Wolfgang Günther, Rolf Drechsler:
Improving EAs for Sequencing Problems. GECCO 2000: 175-180 - [c18]Rolf Drechsler, Wolfgang Günther:
Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. GECCO 2000: 513-518 - [c17]Wolfgang Günther, Rolf Drechsler, Stefan Höreth:
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. ICCD 2000: 383-388 - [c16]Rolf Drechsler, Wolfgang Günther:
Optimization of sequential verification by history-based dynamic minimization of BDDs. ISCAS 2000: 737-740 - [c15]Dragan Jankovic
Lower Bound Sifting for MDDs. ISMVL 2000: 193-198 - [c14]Frank Schmiedle, Wolfgang Günther, Rolf Drechsler:
Dynamic Re-Encoding During MDD Minimization. ISMVL 2000: 239-244 - [c13]Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther:
A Method for Approximate Equivalence Checking. ISMVL 2000: 447-452 - [c12]Rolf Drechsler, Wolfgang Günther, Bernd Becker:
Testability of Circuits Derived from Lattice Diagrams. LATW 2000: 77-81 - [c11]Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Verification of Designs Containing Black Boxes. MBMV 2000: 19-26
1990 – 1999
- 1999
- [c10]Wolfgang Günther, Rolf Drechsler:
Minimization of Free BDDs. ASP-DAC 1999: 323-326 - [c9]Rolf Drechsler, Wolfgang Günther:
Using Lower Bounds During Dynamic BDD Minimization. DAC 1999: 29-32 - [c8]Rolf Drechsler
Generation of Optimal Universal Logic Modules. EUROMICRO 1999: 1080-1085 - [c7]Nicole Drechsler, Wolfgang Günther, Rolf Drechsler:
Efficient Graph Coloring by Evolutionary Algorithms. Fuzzy Days 1999: 30-39 - [c6]Wolfgang Günther, Rolf Drechsler:
Efficient manipulation algorithms for linearly transformed BDDs. ICCAD 1999: 50-54 - [c5]Rolf Drechsler, Wolfgang Günther:
History-Based Dynamic Minimization During BDD Construction. VLSI 1999: 334-345 - [c4]Wolfgang Günther, Rolf Drechsler:
Minimization of BDDs using linear transformations based on evolutionary techniques. ISCAS (1) 1999: 387-390 - [c3]Wolfgang Günther, Rolf Drechsler:
Creating hard problem instances in logic synthesis using exact minimization. ISCAS (6) 1999: 436-439 - 1998
- [c2]Rolf Drechsler, Nicole Drechsler, Wolfgang Günther:
Fast Exact Minimization of BDDs. DAC 1998: 200-205 - [c1]Wolfgang Günther, Rolf Drechsler:
Linear Transformations and Exact Minimization of BDDs. Great Lakes Symposium on VLSI 1998: 325-330
Coauthor Index
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