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"Simultaneous gate sizing and placement."

Wei Chen, Cheng-Ta Hsieh, Massoud Pedram (2000)

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DOI: 10.1109/43.828549

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - https://dblp.org/rec/journals/tcad/ChenHP00
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram:
Simultaneous gate sizing and placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 206-214 (2000)

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