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Gerhard W. Dueck
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2020 – today
- 2023
- [c66]Siri Sahithi Ponangi, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier, Kazuhiro Konno:
Java Runtime Optimization for Copying Arrays on AArch64. MECO 2023: 1-6 - 2022
- [j25]Philipp Niemann
, Alexandre A. A. de Almeida
Template-based mapping of reversible circuits to IBM quantum computers. Microprocess. Microsystems 90: 104487 (2022) - [c65]Aaron Graham, Jean-Philippe Legault, Hillary Soontiens, Julie Brown, Stephen A. MacKay, Gerhard W. Dueck, Kenneth B. Kent, Kazuhiro Konno, Daryl Maier:
Evaluating the Performance of the Eclipse OpenJ9 JVM JIT Compiler on AArch64. CCECE 2022: 411-418 - 2021
- [j24]Alexandre A. A. de Almeida, Gerhard W. Dueck
Adaptive Integer Linear Programming Model for Optimal Qubit Permutation. IEEE Des. Test 38(4): 78-84 (2021) - [j23]D. Michael Miller
Function translations and search-based transformation for MVL reversible circuit synthesis. Sci. Comput. Program. 212: 102704 (2021) - [j22]Arighna Deb
Exploring the Potential Benefits of Alternative Quantum Computing Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1825-1835 (2021) - [c64]Damian Diago D'monte, Georgiy Krylov, Younes Manton, Gerhard W. Dueck, Kenneth B. Kent:
A lightweight code storage container for the eclipse OMR ahead-of-time compiler. CASCON 2021: 93-103 - [c63]Georgiy Krylov, Petar Jelenkovic, Mark Thom, Gerhard W. Dueck, Kenneth B. Kent, Younes Manton, Daryl Maier:
Ahead-of-time compilation in eclipse OMR on example of WebAssembly. CASCON 2021: 237-243 - [c62]D. Michael Miller, Gerhard W. Dueck:
Descending Order Transformation-based Synthesis of MVL Reversible Circuits. ISMVL 2021: 107-112 - 2020
- [c61]Damian Diago D'monte, Georgiy Krylov, Daryl Maier, Gerhard W. Dueck, Kenneth B. Kent:
An ELF-based storage option for the eclipse OMR ahead-of-time compiler. CASCON 2020: 173-178 - [c60]Arighna Deb, Gerhard W. Dueck, Robert Wille:
Towards Exploring the Potential of Alternative Quantum Computing Architectures. DATE 2020: 682-685 - [c59]Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler
Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers. DSD 2020: 401-407 - [c58]Georgiy Krylov, Maria Patrou, Gerhard W. Dueck, Joran Siu:
The Evolution of Garbage Collection in V8: Google's JavaScript Engine. MECO 2020: 1-6 - [c57]Abhijit Taware, Kenneth B. Kent
Cold Object Identification and Segregation using Page Protection and Profiling. MECO 2020: 1-6 - [c56]D. Michael Miller, Gerhard W. Dueck:
Search-Based Transformation Synthesis for 3-Valued Reversible Circuits. RC 2020: 218-236
2010 – 2019
- 2019
- [j21]Alexandre A. A. de Almeida
CNOT Gate Optimizations via Qubit Permutations for IBM's Quantum Architectures. J. Low Power Electron. 15(2): 182-192 (2019) - [c55]Georgiy Krylov, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier, Irwin D'Souza:
Ahead-of-time compilation in OMR: overview and first steps. CASCON 2019: 299-304 - [c54]Alexandre Araujo Amaral de Almeida
CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures. ISMVL 2019: 7-12 - [c53]Alexandre A. A. de Almeida
Efficient Realization of Toffoli and NCV Circuits for IBM QX Architectures. RC 2019: 131-145 - [c52]Alexandre A. A. de Almeida
Finding optimal qubit permutations for IBM's quantum computer architectures. SBCCI 2019: 13 - 2018
- [c51]Scott Ryan Young, Michael Flawn, Gerhard W. Dueck, Kenneth B. Kent, Charlie Gracie:
Persistent memory storage of cold regions in the OpenJ9 Java virtual machine. CASCON 2018: 213-223 - [c50]Mark Thom, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier:
A survey of ahead-of-time technologies in dynamic language environments. CASCON 2018: 275-281 - [c49]Gerhard W. Dueck, Anirban Pathak
Optimization of Circuits for IBM's Five-Qubit Quantum Computers. DSD 2018: 680-684 - [c48]Maria Patrou, Kenneth B. Kent
NUMA Awareness: Improving Thread and Memory Management. SEAA 2018: 119-123 - [c47]Maria Patrou, Md. Mahbub Alam
DISTIL: a distributed in-memory data processing system for location-based services. SIGSPATIAL/GIS 2018: 496-499 - [c46]Alexandre A. A. de Almeida
Efficient Realizations of CNOT gates in IBM's Quantum Computers. ISED 2018: 58-62 - [c45]Alexandre A. A. de Almeida
Reversible Circuit Optimization Based on Tabu Search. ISMVL 2018: 103-108 - [i7]Gerhard W. Dueck, Anirban Pathak, Md. Mazder Rahman, Abhishek Shukla, Anindita Banerjee:
Optimization of Circuits for IBM's five-qubit Quantum Computers. CoRR abs/1810.00129 (2018) - [i6]Evandro C. Ferraz, Jeferson de Lima Muniz, Alexandre C. R. da Silva, Gerhard W. Dueck:
Synthesis of Majority Expressions through Primitive Function Manipulation. CoRR abs/1810.01486 (2018) - 2017
- [j20]Kim T. Briggs, Baoguo Zhou, Gerhard W. Dueck:
Cold object identification in the Java virtual machine. Softw. Pract. Exp. 47(1): 79-95 (2017) - [i5]Martin Lukac, Gerhard W. Dueck, Michitaka Kameyama, Anirban Pathak:
Building a Completely Reversible Computer. CoRR abs/1702.08715 (2017) - 2016
- [j19]Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Ancilla-free synthesis of large reversible functions using binary decision diagrams. J. Symb. Comput. 73: 1-26 (2016) - [j18]Konstantin Nasartschuk, Marcel Dombrowski, Tristan Basa, Md. Mazder Rahman, Kenneth B. Kent
GarCoSim: A Framework for Automated Memory Management Research and Evaluation. EAI Endorsed Trans. Scalable Inf. Syst. 3(9): e4 (2016) - [c44]Marcel Dombrowski, Konstantin Nasartschuk, Kenneth B. Kent
Thread-group based local heap garbage collection in a simulated runtime environment. CCECE 2016: 1-6 - [c43]Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller:
An extension of transformation-based reversible and quantum circuit synthesis. ISCAS 2016: 2290-2293 - [c42]Nils Przigoda
Fault Detection in Parity Preserving Reversible Circuits. ISMVL 2016: 44-49 - [c41]Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits. ISMVL 2016: 144-149 - [c40]Mathias Soeken, Gerhard W. Dueck, D. Michael Miller:
A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. RC 2016: 307-321 - [c39]Md. Mazder Rahman, Konstantin Nasartschuk, Kenneth B. Kent
Trace Files for Automatic Memory Management Systems. VST@SANER 2016: 9-12 - 2015
- [c38]Marcel Dombrowski, Konstantin Nasartschuk, Kenneth B. Kent
A survey on object cache locality in automated memory management systems. CCECE 2015: 349-354 - [c37]Shijie Xu, Qi Guo, Gerhard W. Dueck, David Bremner, Yang Wang:
Metis: a smart memory allocator using historical reclamation information. ICOOOLPS@ECOOP 2015: 6:1-6:9 - [c36]Md. Mazder Rahman, Mathias Soeken, Gerhard W. Dueck:
Dynamic Template Matching with Mixed-Polarity Toffoli Gates. ISMVL 2015: 72-77 - [c35]Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler
Reversible circuit rewriting with simulated annealing. VLSI-SoC 2015: 286-291 - [i4]Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller:
Self-Inverse Functions and Palindromic Circuits. CoRR abs/1502.05825 (2015) - [i3]Kim T. Briggs, Baoguo Zhou, Gerhard W. Dueck:
Cold Object Identification in the Java Virtual Machine. CoRR abs/1508.04753 (2015) - [i2]Md. Mazder Rahman, Gerhard W. Dueck:
Synthesis of Linear Nearest Neighbor Quantum Circuits. CoRR abs/1508.05430 (2015) - 2014
- [j17]Gerhard W. Dueck:
Challenges and advances in Toffoli network optimisation. IET Comput. Digit. Tech. 8(4): 172-177 (2014) - [j16]Md. Mazder Rahman, Gerhard W. Dueck, Joseph D. Horton:
An Algorithm for Quantum Template Matching. ACM J. Emerg. Technol. Comput. Syst. 11(3): 31:1-31:20 (2014) - [c34]Anindita Banerjee, Anirban Pathak
Minimal Designs of Reversible Sequential Elements. RC 2014: 137-148 - [i1]Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler:
Ancilla-free synthesis of large reversible functions using binary decision diagrams. CoRR abs/1408.3955 (2014) - 2013
- [e1]Gerhard W. Dueck, D. Michael Miller:
Reversible Computation - 5th International Conference, RC 2013, Victoria, BC, Canada, July 4-5, 2013. Proceedings. Lecture Notes in Computer Science 7948, Springer 2013, ISBN 978-3-642-38985-6 [contents] - 2012
- [j15]Majid Mohammadi, Aliakbar Niknafs, Mohammad Eshghi, Gerhard W. Dueck:
Design and Optimization of Single and Multiple-Loop Reversible and Quantum Feedback Circuits. J. Circuits Syst. Comput. 21(3) (2012) - [j14]Hadi Hosseini, Gerhard W. Dueck:
Toffoli Gate Implementation Using The Billiard Ball Model. J. Multiple Valued Log. Soft Comput. 19(1-3): 133-147 (2012) - [c33]Md. Mazder Rahman, Gerhard W. Dueck:
An algorithm to find quantum templates. IEEE Congress on Evolutionary Computation 2012: 1-7 - [c32]Gerhard W. Dueck:
Synthesis of Toffoli Networks: Status and Challenges. ISED 2012: 11-16 - [c31]Md. Mazder Rahman, Gerhard W. Dueck:
Optimal Quantum Circuits of Three Qubits. ISMVL 2012: 161-166 - [c30]Md. Mazder Rahman, Gerhard W. Dueck:
Properties of Quantum Templates. RC 2012: 125-137 - 2011
- [j13]Robert Wille
Debugging reversible circuits. Integr. 44(1): 51-61 (2011) - [c29]Md. Mazder Rahman, Anindita Banerjee, Gerhard W. Dueck, Anirban Pathak
Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit. ISMVL 2011: 86-92 - [c28]Md. Mazder Rahman, Gerhard W. Dueck, Anindita Banerjee:
Optimization of Reversible Circuits Using Reconfigured Templates. RC 2011: 43-53 - 2010
- [c27]Sebastian Offermann, Robert Wille
Synthesizing multiplier in reversible logic. DDECS 2010: 335-340 - [c26]Mathias Soeken
Window optimization of reversible and quantum circuits. DDECS 2010: 341-345 - [c25]Hadi Hosseini, Gerhard W. Dueck:
Toffoli Gate Implementation Using the Billiard Ball Model. ISMVL 2010: 173-178 - [c24]Yasaman Sanaee, Gerhard W. Dueck:
ESOP-Based Toffoli Network Generation with Transformations. ISMVL 2010: 276-281
2000 – 2009
- 2009
- [j12]Gerhard W. Dueck:
Editorial. J. Multiple Valued Log. Soft Comput. 15(4): 265 (2009) - [j11]Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
Exact Synthesis of Elementary Quantum Gate Circuits. J. Multiple Valued Log. Soft Comput. 15(4): 283-300 (2009) - [j10]Daniel Große
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 703-715 (2009) - [c23]Robert Wille, Daniel Große
Debugging of Toffoli networks. DATE 2009: 1284-1289 - [c22]D. Michael Miller, Robert Wille
Synthesizing Reversible Circuits for Irreversible Functions. DSD 2009: 749-756 - [c21]Robert Wille
Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194 - 2008
- [j9]Dmitri Maslov
Quantum Circuit Simplification and Level Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 436-444 (2008) - [c20]Robert Wille
Quantified Synthesis of Reversible Logic. DATE 2008: 1015-1020 - [c19]Nathan O. Scott, Gerhard W. Dueck:
Pairwise decomposition of toffoli gates in a quantum circuit. ACM Great Lakes Symposium on VLSI 2008: 231-236 - [c18]Daniel Große, Robert Wille
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219 - [c17]Robert Wille
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225 - 2007
- [j8]Dmitri Maslov
Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12(4): 42 (2007) - [c16]Daniel Große
Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101 - 2006
- [j7]D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck:
Synthesis of Quantum Multiple-Valued Circuits. J. Multiple Valued Log. Soft Comput. 12(5-6): 431-450 (2006) - [c15]Dmitri Maslov, Gerhard W. Dueck:
Level Compaction in Quantum Circuits. IEEE Congress on Evolutionary Computation 2006: 2405-2409 - 2005
- [j6]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Toffoli network synthesis with templates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 807-817 (2005) - [j5]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 765-769 (2005) - [c14]Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck:
Quantum Circuit Simplification Using Templates. DATE 2005: 1208-1213 - 2004
- [j4]Dmitri Maslov, Gerhard W. Dueck:
Reversible cascades with minimal garbage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11): 1497-1509 (2004) - [c13]D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov:
A Synthesis Method for MVL Reversible Logi. ISMVL 2004: 74-80 - 2003
- [c12]D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck:
A transformation based algorithm for reversible logic synthesis. DAC 2003: 318-323 - [c11]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD 2003: 256-261 - [c10]D. Michael Miller, Gerhard W. Dueck:
On the Size of Multiple-Valued Decision Diagrams. ISMVL 2003: 235-240 - [c9]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Simplification of Toffoli Networks via Templates. SBCCI 2003: 53- - 2001
- [j3]Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich
On the number of generators for transeunt triangles. Discret. Appl. Math. 108(3): 309-316 (2001) - [j2]Ping Wang, Gerhard W. Dueck, S. MacMillan:
Using simulated annealing to construct extremal graphs. Discret. Math. 235(1-3): 125-135 (2001) - 2000
- [j1]Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1386-1388 (2000) - [c8]Svetlana N. Yanushkevich
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL 2000: 141-146
1990 – 1999
- 1999
- [c7]Gerhard W. Dueck, Mou Hu, Blair Fraser:
A Super Switch Algebra for Quantum Device Based Systems. ISMVL 1999: 118-124 - 1998
- [c6]Blair Fraser, Gerhard W. Dueck:
Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. ISMVL 1998: 239-244 - 1994
- [c5]Gerhard W. Dueck, Jon T. Butler:
Multiple-Valued Logic Operations with Universal Literals. ISMVL 1994: 73-79 - 1992
- [c4]Gerhard W. Dueck:
Direct Cover MVL Minimization with Cost-Tables. ISMVL 1992: 58-65 - [c3]Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler:
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74 - 1991
- [c2]Gerhard W. Dueck, G. H. John van Rees:
On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. ISMVL 1991: 280-286 - 1990
- [c1]Gerhard W. Dueck, D. Michael Miller:
RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL 1990: 136-143
Coauthor Index
Alexandre A. A. de Almeida
aka: Alexandre Araujo Amaral de Almeida
aka: Alexandre Araujo Amaral de Almeida
Alexandre C. R. da Silva
aka: Alexandre César Rodrigues da Silva
aka: Alexandre César Rodrigues da Silva
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