default search action
DASIP 2016: Rennes, France
- 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, October 12-14, 2016. IEEE 2016, ISBN 979-1-0922-7915-3
- Eduardo Juárez:
Session 1: HEVC in embedded systems. 1 - Ronan Parois, Wassim Hamidouche, Elie Gabriel Mora, Mickaël Raulet, Olivier Déforges:
Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder. 11-17 - Erwan Raffin
, Wassim Hamidouche, Erwan Nogues, Maxime Pelcat, Daniel Ménard:
Scalable HEVC decoder for mobile devices: Trade-off between energy consumption and quality. 18-25 - Alexandre Mercat, Wassim Hamidouche, Maxime Pelcat, Daniel Ménard:
Estimating encoding complexity of a real-time embedded software HEVC codec. 26-33 - Georgios Georgakarakos, Simon Holmbacka, Johan Lilius
Analysis on scalability and energy efficiency of HEVC decoding using task-based programming model. 34-41 - Francesca Palumbo:
Session 2: Architectures for image processing. 42 - Koldo Basterretxea, Unai Martinez-Corral
ELM-based hyperspectral imagery processor for onboard real-time classification. 43-50 - Robin Danilo, Hugues Nono Wouafo, Cyrille Chavet, Vincent Gripon, Laura Conde-Canencia, Philippe Coussy:
Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection. 51-58 - Hamza Bendaoudi, Farida Cheriet, J. M. Pierre Langlois:
Memory efficient Multi-Scale Line Detector architecture for retinal blood vessel segmentation. 59-64 - Lucana Santos
SystemC modelling of lossless compression IP cores for space applications. 65-72 - Diana Goehringer:
Session 3: Method and tools for system design. 73 - Benjamin Tan
A system-level security approach for heterogeneous MPSoCs. 74-81 - Lin Li, Tiziana Fanni
Low power design methodology for signal processing systems using lightweight dataflow techniques. 82-89 - Mehmet Ali Arslan, Flavius Gruian
Code generation for a SIMD architecture with custom memory organisation. 90-97 - Ghislain Takam Tchendjou, Rshdee Alhakim, Emmanuel Simeu:
Fuzzy logic modeling for objective image quality assessment. 98-105 - Morteza Biglari-Abhari:
Session 4: Advanced hardware architectures. 106 - Thibaud Tonnellier
Hardware architecture for lowering the error floor of LTE turbo codes. 107-112 - Mohamad Alfadl Rihani, Jean-Christophe Prévotet
ARM-FPGA based platform for automated adaptive wireless communication systems using partial reconfiguration technique. 113-120 - Erwan Moreac, André Rossi
Crosstalk-aware link power model for Networks-on-Chip. 121-128 - Pierre Langlois:
Session 5: Image processing on multicore plateforms. 129 - Florian Lemaitre, Lionel Lacassagne:
Batched Cholesky factorization for tiny matrices. 130-137 - Sander Smets, Toon Goedemé
Custom processor design for efficient, yet flexible Lucas-Kanade optical flow. 138-145 - José Arnaldo Mascagni de Holanda, João Manuel Paiva Cardoso
A pipelined multi-softcore approach for the HOG algorithm. 146-153 - Daniel Madroñal
Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform. 154-160 - Walter Stechele, Tomasz Kryjak, Lionel Lacassagne, Dominique Houzet, Martin Danek:
Special session 1 automotive parallel computing challenges - architectures, applications and tricks. 161 - Robert Krutsch, Sharath Naidu:
Monte Carlo method based precision analysis of deep convolution nets. 162-167 - Frank Meinl, Martin Kunert, Holger Blume
Hardware acceleration of Maximum-Likelihood angle estimation for automotive MIMO radars. 168-175 - Dominique Houzet, Virginie Fresse, Hubert Konik:
FPGA memory optimization for real-time imaging. 176-182 - Mateusz Komorkiewicz, Krzysztof Turek, Pawel Skruch, Tomasz Kryjak
FPGA-based Hardware-in-the-Loop environment using video injection concept for camera-based systems in automotive applications. 183-190 - Wenhao Wang, Fabrice Camut, Benoît Miramond
Generation of schedule tables on multi-core systems for AUTOSAR applications. 191-198 - Patrice Delmas, Rachel Ababou:
Special session 2 Computer vision and Image analysis. 199 - Khadija Hadj Salem
Memory management in embedded vision systems: Optimization problems and solution methods. 200-207 - Judicael Menant, Guillaume Gautier, Jean-François Nezan, Muriel Pressigout, Luce Morin:
A comparison of cost construction methods onto a C6678 platform for stereo matching. 208-214 - Trevor Gee, Patrice Delmas, Sylvain Joly, Valentin Baron, Rachel Ababou, Jean-François Nezan:
A dedicated lightweight binocular stereo system for real-time depth-map generation. 215-221 - Pierre Langlois, Kevin J. M. Martin, Eduardo Juárez Martínez:
Demo Night. 222 - Mohamed Mourad Hafidhi, Emmanuel Boutillon, Arnaud Dion
Demo: Localisation in a faulty digital GPS receiver. 223-224 - Tian Xia, Mohamad Alfadl Rihani, Jean-Christophe Prévotet
Demo: Ker-ONE: Embedded virtualization approach with dynamic reconfigurable accelerators management. 225-226 - Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran
Demo: Efficient delay and apodization for on-FPGA 3D ultrasound. 227-228 - Fayçal Ait Aoudia, Matthieu Gautier, Olivier Berder:
Demo abstract: How fuzzy logic can enhance energy management in Wireless Sensor nodes equipped by energy harvesters and wake-up radios. 229-230 - Nicolas Cuperlier, Frédéric Demelo, Benoît Miramond
FPGA-based bio-inspired architecture for multi-scale attentional vision. 231-232 - Ali Hassan El Moussawi, Steven Derrien:
Demo: SLP-aware word length optimization. 233-234 - Ronan Parois, Wassim Hamidouche, Elie Gabriel Mora, Mickaël Raulet, Olivier Déforges:
Demo: UHD live video streaming with a real-time scalable HEVC encoder. 235-236 - Rubén Salvador
Demo: HELICoiD tool demonstrator for real-time brain cancer detection. 237-238 - Théotime Bollengier, Mohamad Najem, Jean-Christophe Le Lann, Loïc Lagadec
Demo: Overlay architectures for heterogeneous FPGA cluster management. 239-240 - Mai-Thanh Tran, Emmanuel Casseau, Matthieu Gautier:
Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard. 241-242 - Pierre-Edouard Beaucamps, Frédéric Blanc Kalray:
Demo: MPPA® manycore processor towards future ADAS system solutions. 243-244 - Carlo Sau
Demo: Reconfigurable Platform Composer Tool. 245-246
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-14 21:12 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: