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Paolo Meloni
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2020 – today
- 2024
- [j31]Paola Busia
, Andrea Cossettini
Reducing False Alarms in Wearable Seizure Detection With EEGformer: A Compact Transformer Model for MCUs. IEEE Trans. Biomed. Circuits Syst. 18(3): 608-621 (2024) - [c51]Paolo Meloni, Paola Busia, Gianluca Leone
Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach. ARC 2024: 296-302 - [c50]Matteo Antonio Scrugli
sEMG-Based Gesture Recognition with Spiking Neural Networks on Low-Power FPGA. DASIP 2024: 15-26 - [c49]Matteo Antonio Scrugli, Paola Busia, Gianluca Leone, Paolo Meloni:
On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis. DATE 2024: 1-6 - [c48]Paola Busia
Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry. UMAP (Adjunct Publication) 2024 - [i6]Paola Busia, Matteo Antonio Scrugli, Victor Jean-Baptiste Jung, Luca Benini, Paolo Meloni:
A Noisy Beat is Worth 16 Words: a Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers. CoRR abs/2402.10748 (2024) - 2023
- [j30]Gianluca Leone
On-FPGA Spiking Neural Networks for End-to-End Neural Decoding. IEEE Access 11: 41387-41399 (2023) - [j29]Matteo Antonio Scrugli
A Microcontroller-Based Platform for Cognitive Tracking of Sensorimotor Training. IEEE Access 11: 70778-70794 (2023) - [j28]Francesco Ratto
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators. J. Signal Process. Syst. 95(9): 1091-1113 (2023) - [c47]Gianluca Leone
On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding. ARC 2023: 185-199 - [c46]Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni:
Spiking Neural Networks for Integrated Reach-to-Grasp Decoding on FPGAs. BioCAS 2023: 1-5 - 2022
- [j27]Matteo Antonio Scrugli
An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things. IEEE Access 10: 1688-1705 (2022) - [j26]Paola Busia
Target-Aware Neural Architecture Search and Deployment for Keyword Spotting. IEEE Access 10: 40687-40700 (2022) - [j25]Gianluca Leone
A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA. IEEE Access 10: 76780-76793 (2022) - [c45]Paola Busia, Andrea Cossettini, Thorir Mar Ingolfsson, Simone Benatti
EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices. BioCAS 2022: 640-644 - [c44]Paola Busia, Ilias Theodorakopoulos, Vasileios K. Pothos, Nikos Fragoulis, Paolo Meloni:
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems. DASIP 2022: 45-56 - [c43]Matteo Antonio Scrugli
An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition. DASIP 2022: 149-161 - [c42]Paolo Meloni, Alessandro Serpi
Integration of Energy Storage Systems within Modular Multilevel Converters for Medium-Voltage Distribution Networks. IECON 2022: 1-6 - [i5]Matteo Antonio Scrugli, Bojan Blazica, Paolo Meloni:
An adaptable cognitive microcontroller node for fitness activity recognition. CoRR abs/2201.05110 (2022) - 2021
- [j24]Paola Busia
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge. IEEE Access 9: 133289-133308 (2021) - [c41]Georg Buchgeher, Gerald Czech, Adriano Souza Ribeiro, Werner Kloihofer, Paolo Meloni, Paola Busia, Gianfranco Deriu, Maura Pintor
Task-Specific Automation in Deep Learning Processes. DEXA Workshops 2021: 159-169 - [i4]Frank Hannig, Paolo Meloni, Matteo Spallanzani, Matthias Ziegler:
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). CoRR abs/2102.00818 (2021) - [i3]Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni:
An adaptive cognitive sensor node for ECG monitoring in the Internet of Medical Things. CoRR abs/2106.06498 (2021) - 2020
- [j23]Gianluca Leone
ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays. IEEE Access 8: 218145-218160 (2020) - [j22]Paolo Meloni
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge. IEEE Embed. Syst. Lett. 12(2): 62-65 (2020) - [j21]Marco Carreras
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 348-361 (2020) - [c40]S. Loddo, M. Soccol, A. Perra, M. Ucchesu, Paolo Meloni, Massimo Barbaro, Mauro Lo Cascio, C. Sirca:
Biosensing IoT Platform for Water Management in Vineyards. ISCAS 2020: 1-4 - [i2]Marco Carreras, Gianfranco Deriu, Luigi Raffo, Luca Benini, Paolo Meloni:
Optimizing Temporal Convolutional Network inference on FPGA-based accelerators. CoRR abs/2005.03775 (2020)
2010 – 2019
- 2019
- [c39]Paolo Meloni, Daniela Loi, Paola Busia, Gianfranco Deriu, Andy D. Pimentel
Optimization and deployment of CNNs at the edge: the ALOHA experience. CF 2019: 326-332 - [c38]Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo
A runtime-adaptive cognitive IoT node for healthcare monitoring. CF 2019: 350-357 - [c37]Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni:
Runtime-Adaptive Cognitive IoT Nodes. CPS Summer School, PhD Workshop 2019: 39-50 - [c36]Marco Carreras, Gianfranco Deriu, Paolo Meloni:
Flexible Acceleration of Convolutions on FPGAs: NEURAghe 2.0. CPS Summer School, PhD Workshop 2019: 60-71 - [c35]Paolo Meloni, Antonio Garufi, Gianfranco Deriu, Marco Carreras, Daniela Loi:
CNN hardware acceleration on a low-power and low-cost APSoC. DASIP 2019: 7-12 - [c34]Sara Zaher, Davide Lonardoni, Fabio Boi
A Closed-Loop System Processing High-Density Electrical Recordings and Visual Stimuli to Study Retinal Circuits Properties. NER 2019: 652-656 - 2018
- [j20]Giovanni Pietro Seu
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays. IEEE Trans. Biomed. Circuits Syst. 12(4): 839-850 (2018) - [j19]Paolo Meloni
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. ACM Trans. Reconfigurable Technol. Syst. 11(3): 18:1-18:24 (2018) - [c33]Paolo Meloni
ALOHA: an architectural-aware framework for deep learning at the edge. INTESA@ESWEEK 2018: 19-26 - [c32]Paolo Meloni, Daniela Loi, Gianfranco Deriu, Andy D. Pimentel
Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project. ICM 2018: 52-55 - 2017
- [j18]Carlo Sau
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing. IEEE Embed. Syst. Lett. 9(3): 65-68 (2017) - [j17]Paolo Meloni, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs. J. Syst. Archit. 76: 89-101 (2017) - [j16]Francesca Palumbo
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy. J. Signal Process. Syst. 87(1): 81-106 (2017) - [c31]Giovanni Pietro Seu
On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration. IPDPS Workshops 2017: 175-183 - [c30]Francesca Palumbo
Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture. IPDPS Workshops 2017: 247-250 - [i1]Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini:
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. CoRR abs/1712.00994 (2017) - 2016
- [j15]Francesca Palumbo
Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures. J. Electr. Comput. Eng. 2016: 4237350:1-4237350:27 (2016) - [j14]Paolo Meloni, Francesca Palumbo
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation. Microprocess. Microsystems 43: 67-80 (2016) - [j13]Giuseppe Tuveri, Paolo Meloni, Francesca Palumbo
On-the-fly adaptivity for process networks over shared-memory platforms. Microprocess. Microsystems 46: 240-254 (2016) - [j12]Carlo Sau
Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J. Signal Process. Syst. 85(1): 143-165 (2016) - [c29]Paolo Meloni, Gianfranco Deriu, Francesco Conti
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA. Conf. Computing Frontiers 2016: 376-383 - [c28]Tiziana Fanni
Power and clock gating modelling in coarse grained reconfigurable systems. Conf. Computing Frontiers 2016: 384-391 - [c27]Carlo Sau
Demo: Reconfigurable Platform Composer Tool. DASIP 2016: 245-246 - [c26]Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. ReConFig 2016: 1-8 - [c25]Francesca Palumbo
Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms. SiPS 2016: 127-129 - 2015
- [c24]Paolo Meloni, Giuseppe Tuveri, Danilo Pani
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding. DASIP 2015: 1-8 - [c23]Tiziana Fanni
Power modelling for saving strategies in coarse grained reconfigurable systems. ReConFig 2015: 1-4 - [c22]Carlo Sau
Reconfigurable coprocessors synthesis in the MPEG-RVC domain. ReConFig 2015: 1-8 - 2014
- [j11]Nicola Carta, Paolo Meloni
A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(2): 230-241 (2014) - [j10]Francesca Palumbo
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms. J. Real Time Image Process. 9(1): 233-249 (2014) - [c21]Paolo Meloni
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks. MES 2014: 25-32 - [c20]Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti:
Online process transformation for polyhedral process networks in shared-memory MPSoCs. MECO 2014: 92-97 - 2013
- [j9]Onur Derin, Emanuele Cannella, Giuseppe Tuveri, Paolo Meloni
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project. Microprocess. Microsystems 37(6-7): 515-529 (2013) - [j8]Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni
ASAM: Automatic architecture synthesis and application mapping. Microprocess. Microsystems 37(8-C): 1002-1019 (2013) - [c19]Paolo Meloni, Christophe Jégo:
Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy. DASIP 2013: 8 - [c18]Giuseppe Tuveri, Simone Secchi, Paolo Meloni, Luigi Raffo, Emanuele Cannella:
A runtime adaptive H.264 video-decoding MPSoC platform. DASIP 2013: 149-156 - [c17]Onur Derin, Prasanth Kuncheerath Ramankutty, Paolo Meloni, Giuseppe Tuveri:
A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs. PECCS 2013: 262-269 - 2012
- [j7]Onur Derin, Prasanth Kuncheerath Ramankutty, Paolo Meloni, Emanuele Cannella:
Towards Self-Adaptive KPN Applications on NoC-Based MPSoCs. Adv. Softw. Eng. 2012: 172674:1-172674:16 (2012) - [j6]Paolo Meloni
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. VLSI Design 2012: 580584:1-580584:16 (2012) - [j5]Emanuele Cannella, Onur Derin, Paolo Meloni
Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks. VLSI Design 2012: 987209:1-987209:17 (2012) - [c16]Sebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo
Exploiting binary translation for fast ASIP design space exploration on FPGAs. DATE 2012: 566-569 - [c15]Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni
ASAM: Automatic Architecture Synthesis and Application Mapping. DSD 2012: 216-225 - [c14]Paolo Meloni
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach. DSD 2012: 517-524 - [c13]Paolo Meloni
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems. ICSAMOS 2012: 310-317 - 2011
- [c12]Emanuele Cannella, Lorenzo Di Gregorio, Leandro Fiorin, Menno Lindwer, Paolo Meloni, Olaf Neugebauer, Andy D. Pimentel
Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not? ESTIMedia 2011: 120-129 - 2010
- [j4]Paolo Meloni
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures. IEEE Embed. Syst. Lett. 2(1): 5-9 (2010) - [c11]Simone Secchi, Paolo Meloni
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures. ISPASS 2010: 194-202 - [c10]Paolo Meloni
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. VLSI-SoC 2010: 43-48
2000 – 2009
- 2007
- [j3]Federico Angiolini, Paolo Meloni
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 421-434 (2007) - [j2]Srinivasan Murali, David Atienza
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 869-880 (2007) - [j1]Paolo Meloni
Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI Design 2007: 50285:1-50285:12 (2007) - [c9]Paolo Meloni
On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs. DSD 2007: 556-562 - [c8]Antonio Pullini, Federico Angiolini, Paolo Meloni
NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282 - 2006
- [c7]Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo
Contrasting a NoC and a traditional interconnect fabric with layout awareness. DATE 2006: 124-129 - [c6]Srinivasan Murali, Paolo Meloni
Designing application-specific networks on chips with floorplan information. ICCAD 2006: 355-362 - [c5]Paolo Meloni
Area and Power Modeling Methodologies for Networks-on-Chip. Nano-Net 2006: 1-7 - [c4]Paolo Meloni
Routing Aware Switch Hardware Customization for Networks on Chips. Nano-Net 2006: 1-5 - [c3]Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. VLSI-SoC 2006: 158-163 - [c2]Srinivasan Murali, Paolo Meloni
Designing Routing and Message-Dependent Deadlock Free Networks on Chips. VLSI-SoC (Selected Papers) 2006: 337-355 - 2005
- [c1]Federico Angiolini, Paolo Meloni, Luca Benini, Salvatore Carta, Luigi Raffo:
Networks on Chips: A Synthesis Perspective. PARCO 2005: 745-752
Coauthor Index
[j30] [j29] [j28] [c47] [c46] [j27] [j26] [j25] [j24] [i3] [j23] [j21] [i2] [c38] [c37] [j20] [j19] [j18] [j17] [c31] [c30] [i1] [j15] [j14] [j13] [j12] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [j11] [j10] [c21] [c20] [j9] [j8] [c18] [j6] [c16] [c15] [c14] [c13] [j4] [c11] [c10] [j3] [j2] [j1] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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last updated on 2024-10-07 22:23 CEST by the dblp team
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