default search action
J. M. Pierre Langlois
Pierre Langlois 0001
Person information
- affiliation: Polytechnique Montréal
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [c64]Aymen-Alaeddine Zeghaida, Dinesh Daultani, J. M. Pierre Langlois, Jean-Pierre David:
Scalable Low-Complexity Implementation of Constant Matrix Multiplication Circuits. MWSCAS 2024: 357-361 - [i13]Mobin Vaziri, Shervin Vakili, M. Mehdi Rahimifar, J. M. Pierre Langlois:
HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators. CoRR abs/2407.19165 (2024) - 2023
- [j28]Thomas Luinaud
, J. M. Pierre Langlois
Symbolic Analysis for Data Plane Programs Specialization. ACM Trans. Archit. Code Optim. 20(1): 1:1-1:21 (2023) - [c63]Amirali Ebrahimi, Vineeth Narayan Pullu, J. M. Pierre Langlois, Jean-Pierre David:
Iterative pruning algorithm for efficient look-up table implementation of binary neural networks. NEWCAS 2023: 1-5 - [i12]Shervin Vakili, Mobin Vaziri, Amirhossein Zarei, J. M. Pierre Langlois:
Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration. CoRR abs/2310.10053 (2023) - 2022
- [c62]Moussa Traore, J. M. Pierre Langlois, Jean-Pierre David:
ASIP Accelerator for LUT-based Neural Networks Inference. NEWCAS 2022: 524-528 - 2021
- [j27]Mehdi Ahmadi
CARLA: A Convolution Accelerator With a Reconfigurable and Low-Energy Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3184-3196 (2021) - [c61]Thomas Luinaud
Design Principles for Packet Deparsers on FPGAs. FPGA 2021: 280-286 - [i11]Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria:
Design Principles for Packet Deparsers on FPGAs. CoRR abs/2103.07750 (2021) - 2020
- [j26]Ahmed M. Abdelsalam
POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. J. Signal Process. Syst. 92(1): 95-107 (2020) - [c60]Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois:
Unleashing the Power of FPGAs as Programmable Switches. FPGA 2020: 311 - [c59]Thomas Luinaud
Bridging the Gap: FPGAs as Programmable Switches. HPSR 2020: 1-7 - [c58]Sivakumar Chidambaram, Pierre Langlois, Jean-Pierre David:
PoET-BiN: Power Efficient Tiny Binary Neurons. MLSys 2020 - [c57]Mehdi Ahmadi, Shervin Vakili, J. M. Pierre Langlois:
An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs. NEWCAS 2020: 214-217 - [c56]Mehdi Ahmadi, Shervin Vakili, J. M. Pierre Langlois:
Heterogeneous Distributed SRAM Configuration for Energy-Efficient Deep CNN Accelerators. NEWCAS 2020: 287-290 - [i10]Mehdi Ahmadi, Shervin Vakili, J. M. Pierre Langlois:
An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs. CoRR abs/2002.07711 (2020) - [i9]Sivakumar Chidambaram, J. M. Pierre Langlois, Jean-Pierre David:
PoET-BiN: Power Efficient Tiny Binary Neurons. CoRR abs/2002.09794 (2020) - [i8]Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois:
Bridging the Gap: FPGAs as Programmable Switches. CoRR abs/2004.07733 (2020) - [i7]Mehdi Ahmadi, Shervin Vakili, J. M. Pierre Langlois:
CARLA: A Convolution Accelerator with a Reconfigurable and Low-Energy Architecture. CoRR abs/2010.00627 (2020)
2010 – 2019
- 2019
- [j25]Thibaut Stimpfling
SHIP: A Scalable High-Performance IPv6 Lookup Algorithm That Exploits Prefix Characteristics. IEEE/ACM Trans. Netw. 27(4): 1529-1542 (2019) - [c55]Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois:
POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests. DASIP 2019: 13-18 - [c54]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design. FCCM 2019: 218-226 - [i6]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design. CoRR abs/1903.06693 (2019) - 2018
- [j24]Shervin Vakili
Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Commun. 12(7): 868-875 (2018) - [j23]Hamza Bendaoudi
Flexible architectures for retinal blood vessel segmentation in high-resolution fundus images. J. Real Time Image Process. 15(1): 31-42 (2018) - [j22]Ali Mosleh
Explicit Ringing Removal in Image Deblurring. IEEE Trans. Image Process. 27(2): 580-593 (2018) - [c53]Thibaut Stimpfling, J. M. Pierre Langlois, Normand Bélanger, Yvon Savaria:
A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis. CCGrid 2018: 402-411 - [c52]Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois:
POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA. DASIP 2018: 19-24 - [c51]Sivakumar Chidambaram, Alexandre Riviello, J. M. Pierre Langlois, Jean-Pierre David:
Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors. DASIP 2018: 94-99 - [c50]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. FPGA 2018: 147-152 - [c49]Mathieu Léonardon, Camille Leroux, David Binet, J. M. Pierre Langlois, Christophe Jégo, Yvon Savaria:
Custom Low Power Processor for Polar Decoding. ISCAS 2018: 1-5 - [c48]Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois:
Extern Objects in P4: an ROHC Header Compression Scheme Case Study. NetSoft 2018: 517-522 - [c47]Mehdi Ahmadi, Shervin Vakili
Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy. NEWCAS 2018: 125-129 - [c46]Ahmed M. Abdelsalam, Felix Boulet, Gabriel Demers, J. M. Pierre Langlois, Farida Cheriet:
An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs. ReConFig 2018: 1-6 - 2017
- [j21]Shuli Gao, Dhamin Al-Khalili
Efficient Realization of BCD Multipliers Using FPGAs. Int. J. Reconfigurable Comput. 2017: 2410408:1-2410408:12 (2017) - [c45]Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini:
Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. CCECE 2017: 1-6 - [c44]Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet:
A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation. FCCM 2017: 168-171 - [c43]Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet:
Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only). FPGA 2017: 287 - [c42]Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois:
An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only). FPGA 2017: 287-288 - [c41]Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois:
An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search. ACM Great Lakes Symposium on VLSI 2017: 423-426 - [c40]Ideh Sarbishei, Shervin Vakili
Scalable memory-less architecture for string matching with FPGAs. ISCAS 2017: 1-4 - [i5]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. CoRR abs/1711.06613 (2017) - [i4]Thibaut Stimpfling, Normand Bélanger, J. M. Pierre Langlois, Yvon Savaria:
SHIP: A Scalable High-performance IPv6 Lookup Algorithm that Exploits Prefix Characteristics. CoRR abs/1711.09155 (2017) - 2016
- [j20]Shervin Vakili
Accuracy-aware processor customisation for fixed-point arithmetic. IET Comput. Digit. Tech. 10(1): 1-11 (2016) - [j19]Rana Farah
Computing a rodent's diary. Signal Image Video Process. 10(3): 567-574 (2016) - [j18]Lama Séoud, Thomas Hurtut, Jihed Chelbi, Farida Cheriet, J. M. Pierre Langlois:
Red Lesion Detection Using Dynamic Shape Features for Diabetic Retinopathy Screening. IEEE Trans. Medical Imaging 35(4): 1116-1126 (2016) - [c39]Shervin Vakili
Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm. ANCS 2016: 37-42 - [c38]Alexsandre B. Lacroix, J. M. Pierre Langlois, François-Raymond Boyer, Antoine Gosselin, Guy Bois:
Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems. ANCS 2016: 121-122 - [c37]Hamza Bendaoudi, Farida Cheriet, J. M. Pierre Langlois:
Memory efficient Multi-Scale Line Detector architecture for retinal blood vessel segmentation. DASIP 2016: 59-64 - [c36]Pierre Langlois:
Session 5: Image processing on multicore plateforms. DASIP 2016: 129 - [c35]Pierre Langlois, Kevin J. M. Martin, Eduardo Juárez Martínez:
Demo Night. DASIP 2016: 222 - [c34]Qifeng Gan, Lama Seoud, Houssem Ben Tahar, J. M. Pierre Langlois:
Memory efficient and constant time 2D-recursive spatial averaging filter for embedded implementations. Real-Time Image and Video Processing 2016: 989705 - [i3]Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet:
Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter. CoRR abs/1609.07750 (2016) - [i2]Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois:
Extern Objects in P4: an ROHC Compression Case Study. CoRR abs/1611.05943 (2016) - [i1]Hamza Bendaoudi, Farida Cheriet, J. M. Pierre Langlois:
Memory Efficient Multi-Scale Line Detector Architecture for Retinal Blood Vessel Segmentation. CoRR abs/1612.09524 (2016) - 2015
- [j17]Guillaume-Alexandre Bilodeau
Body temperature measurement of an animal by tracking in biomedical experiments. Signal Image Video Process. 9(2): 251-259 (2015) - [c33]Shervin Vakili
Designing customized microprocessors for fixed-point computation. AHS 2015: 1 - [c32]Ali Mosleh, Paul Green, Emmanuel Onzon, Isabelle Bégin, J. M. Pierre Langlois:
Camera intrinsic blur kernel estimation: A reliable framework. CVPR 2015: 4961-4968 - [c31]Hamza Bendaoudi, Qifeng Gan, Farida Cheriet, Houssem Ben Tahar, J. M. Pierre Langlois:
A run-length encoding co-processor for retinal image texture analysis. ReConFig 2015: 1-6 - 2014
- [j16]Qifeng Gan, J. M. Pierre Langlois, Yvon Savaria:
A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems. Circuits Syst. Signal Process. 33(11): 3591-3602 (2014) - [j15]Rana Farah, Qifeng Gan, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau
A computationally efficient importance sampling tracking algorithm. Mach. Vis. Appl. 25(7): 1761-1777 (2014) - [j14]Qifeng Gan, J. M. Pierre Langlois, Yvon Savaria:
Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations. J. Signal Process. Syst. 75(3): 191-202 (2014) - [c30]Hamza Bendaoudi, Farida Cheriet, Houssem Ben Tahar, J. M. Pierre Langlois:
A scalable hardware architecture for retinal blood vessel detection in high resolution fundus images. DASIP 2014: 1-6 - [c29]Ali Mosleh, J. M. Pierre Langlois, Paul Green:
Image Deconvolution Ringing Artifact Detection and Removal via PSF Frequency Analysis. ECCV (4) 2014: 247-262 - [c28]Lama Séoud, Timothée Faucon, Thomas Hurtut, Jihed Chelbi, Farida Cheriet, J. M. Pierre Langlois:
Automatic detection of microaneurysms and haemorrhages in fundus images using dynamic shape features. ISBI 2014: 101-104 - [c27]Mahnaz Fasih, J. M. Pierre Langlois, Houssem Ben Tahar, Farida Cheriet:
Retinal image quality assessment using generic features. Medical Imaging: Computer-Aided Diagnosis 2014: 90352Z - [c26]Thalie Keklikian, J. M. Pierre Langlois, Yvon Savaria:
A memory transaction model for Sparse Matrix-Vector multiplications on GPUs. NEWCAS 2014: 309-312 - 2013
- [j13]Shervin Vakili
Customised soft processor design: a compromise between architecture description languages and parameterisable processors. IET Comput. Digit. Tech. 7(3) (2013) - [j12]Shervin Vakili
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(12): 1853-1865 (2013) - [j11]Rana Farah, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau
Catching a Rat by Its Edglets. IEEE Trans. Image Process. 22(2): 668-678 (2013) - [c25]Diana Carolina Gil, J. M. Pierre Langlois, Yvon Savaria:
Accelerating a modified Gaussian pyramid with a customized processor. DASIP 2013: 259-264 - [c24]Shervin Vakili
Finite-precision error modeling using affine arithmetic. ICASSP 2013: 2591-2595 - [c23]Qifeng Gan, J. M. Pierre Langlois, Yvon Savaria:
A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor. MWSCAS 2013: 1415-1418 - 2012
- [j10]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Comput. Digit. Tech. 6(6): 372-383 (2012) - [j9]Guillaume-Alexandre Bilodeau
Body temperature estimation of a moving subject from thermographic images. Mach. Vis. Appl. 23(2): 299-311 (2012) - [j8]P. Aubertin, J. M. Pierre Langlois, Yvon Savaria:
Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2031-2043 (2012) - 2011
- [c22]Guillaume-Alexandre Bilodeau
Where is the rat? Tracking in low contrast thermographic images. CVPR Workshops 2011: 55-60 - [c21]Rana Farah, Qifeng Gan, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau
A tracking algorithm suitable for embedded systems implementation. ICECS 2011: 256-259 - [c20]Shervin Vakili
Customized embedded processor design for global photographic tone mapping. ICECS 2011: 382-385 - [c19]Jacques Laurent Athow, Côme Rozon, Dhamin Al-Khalili, J. M. Pierre Langlois:
A CNFET-based characterization framework for digital circuits. ICECS 2011: 681-684 - [c18]Simon Rajotte, Diana Carolina Gil, J. M. Pierre Langlois:
Combining ISA extensions and subsetting for improved ASIP performance and cost. ISCAS 2011: 653-656 - [c17]Diana Carolina Gil, Rana Farah, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau
Comparative analysis of contrast enhancement algorithms in surveillance imaging. ISCAS 2011: 849-852 - [c16]Rana Farah, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau
RAT: Robust animal tracking. ROSE 2011: 65-70 - 2010
- [j7]Azizul Islam, Umar Iqbal
Implementation methodology of embedded land vehicle positioning using an integrated GPS and multi sensor system. Integr. Comput. Aided Eng. 17(1): 69-83 (2010) - [j6]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. J. Signal Process. Syst. 58(1): 3-15 (2010) - [c15]J. C. F. Allaire, J. M. Pierre Langlois, Gilles Labonté, Mohamed Tarbouchi:
Two-tiered Resolution Real-Time Path Evaluation. IJCCI (ICEC) 2010: 321-326
2000 – 2009
- 2009
- [c14]Guillaume-Alexandre Bilodeau, Maxime Levesque, J. M. Pierre Langlois, Pablo Lema, Lionel Carmant:
Thermographic Body Temperature Measurement using a Mean-Shift Tracker. BIOSIGNALS 2009: 18-24 - [c13]Azizul Islam, J. M. Pierre Langlois, Aboelmagd Noureldin
A design methodology for the implementation of embedded vehicle navigation systems. EIT 2009: 297-300 - 2008
- [c12]Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois:
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. ICCD 2008: 255-259 - [c11]Marc-André Daigneault, J. M. Pierre Langlois, Jean-Pierre David:
Application Specific Instruction set processor specialized for block motion estimation. ICCD 2008: 266-271 - [c10]Man Yan Kong, J. M. Pierre Langlois, Dhamin Al-Khalili:
Efficient FPGA implementation of complex multipliers using the logarithmic number system. ISCAS 2008: 3154-3157 - [c9]Atousa Torabi, Guillaume-Alexandre Bilodeau
Measuring an Animal Body Temperature in Thermographic Video Using Particle Filter Tracking. ISVC (1) 2008: 1081-1091 - 2007
- [j5]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
Optimised realisations of large integer multipliers and squarers using embedded blocks. IET Comput. Digit. Tech. 1(1): 9-16 (2007) - [j4]Hossein Mahvash Mohammadi, J. M. Pierre Langlois, Yvon Savaria:
A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Trans. Consumer Electron. 53(3): 1117-1124 (2007) - [c8]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP 2007: 18-23 - 2006
- [j3]J. M. Pierre Langlois, Dhamin Al-Khalili:
Carry-free approximate squaring functions with O(n) complexity and O(1) delay. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 374-378 (2006) - [c7]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. AICCSA 2006: 248-254 - [c6]Nasreddine Hireche, J. M. Pierre Langlois, Gabriela Nicolescu:
Survey of Biological High Performance Computing: Algorithms, Implementations and Outlook Research. CCECE 2006: 1926-1929 - [c5]Hossein Mahvash Mohammadi, J. M. Pierre Langlois, Yvon Savaria:
A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation. ICECS 2006: 459-462 - [c4]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. SoCC 2006: 21-24 - 2003
- [j2]J. M. Pierre Langlois, Dhamin Al-Khalili:
Novel approach to the design of direct digital frequency synthesizers based on linear interpolation. IEEE Trans. Circuits Syst. II Express Briefs 50(9): 567-578 (2003) - [c3]J. M. Pierre Langlois, Dhamin Al-Khalili:
Low power direct digital frequency synthesizers in 0.18 μm CMOS. CICC 2003: 283-286 - 2002
- [j1]J. M. Pierre Langlois, Dhamin Al-Khalili, Robert J. Inkol:
Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation. J. VLSI Signal Process. 32(3): 237-254 (2002) - [c2]J. M. Pierre Langlois, Dhamin Al-Khalili:
A low power direct digital frequency synthesizer with 60 dBc spectral purity. ACM Great Lakes Symposium on VLSI 2002: 166-171 - [c1]J. M. Pierre Langlois, Dhamin Al-Khalili:
Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity. ISCAS (5) 2002: 361-364
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-11 18:19 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: