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Bertrand Le Gal
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2020 – today
- 2024
- [c76]Antoine Siebert, Guillaume Ferré, Bertrand Le Gal, Aurélien Fourny:
Joint Blind Estimation and Equalization Method Based on Deep Learning for Fast Fading Channels. NewCAS 2024: 153-157 - [i1]Juliette Pottier, Thomas Nieddu, Bertrand Le Gal, Sébastien Pillement, Maria Méndez Real:
RISC-V processor enhanced with a dynamic micro-decoder unit. CoRR abs/2406.14999 (2024) - 2023
- [b1]Bertrand Le Gal:
Adéquation Algorithme Architecture - Approches matérielles et logicielles pour les applications de communications numériques. (Algorithm Architecture Matching - Hardware and software approaches for digital communications applications). University of Bordeaux, France, 2023 - [j33]Clémence Gillet, Adrien F. Vincent
, Bertrand Le Gal
A High-Level Methodology to Evaluate and Optimize Digital Architectures Targeting Spike Encoding. IEEE Access 11: 120654-120665 (2023) - [j32]Bertrand Le Gal
High-performance hard-input LDPC decoding on multi-core devices for optical space links. J. Syst. Archit. 137: 102832 (2023) - [j31]Camille Monière
Real-time energy-efficient software and hardware implementations of a QCSP communication system. J. Syst. Archit. 141: 102933 (2023) - [c75]Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal
Securing a RISC-V architecture: A dynamic approach. DATE 2023: 1-5 - [c74]Hugues Almorin, Bertrand Le Gal, Christophe Jégo, Vincent Kissel:
Model Based Design of FMCW Radar Processing Systems on FPGA Platforms. DSD 2023: 24-29 - [c73]Denis Shemonaev, Bertrand Le Gal, Christophe Jégo, Anthony Besseau:
Implementation of an Assignment Algorithm for Object Tracking on a FPGA MPSoC. DSD 2023: 373-380 - [c72]Matthieu Magnant, Mohamed Amine Ben Temim, Bertrand Le Gal, Guillaume Ferré, Florian Collard:
Real-Time Low-Earth Orbit Detector Implementation for Chirp-Based Preamble Communication Systems. LATINCOM 2023: 1-6 - [c71]Antoine Siebert, Guillaume Ferré, Bertrand Le Gal, Aurélien Fourny:
The Smart Kalman Filter: A Deep Learning-Based Approach for Time-Varying Channel Estimation. PIMRC 2023: 1-6 - 2022
- [c70]Clémence Gillet, Adrien F. Vincent, Bertrand Le Gal, Sylvain Saïghi:
Flexible design methodology for spike encoding implementation on FPGA. BioCAS 2022: 379-383 - [c69]Bertrand Le Gal
High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices. DASIP 2022: 3-15 - [c68]Camille Monière
Efficient Software and Hardware Implementations of a QCSP Communication System. DASIP 2022: 29-41 - [c67]Hugues Almorin, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo, Vincent Kissel:
High-throughput FFT architectures using HLS tools. ICECS 2022 2022: 1-4 - [c66]Léa Volpin, Bertrand Le Gal, Guillaume Ferré:
Efficient LoRa-like Transmitter Stacks for SDR Applications. ICECS 2022 2022: 1-4 - [c65]Logan Saint-Germain, Bertrand Le Gal, Fabien Baldacci, Jérémie Crenne, Christophe Jégo, Sebastien Loty:
Methodology to Adapt Neural Network on Constrained Device at Topology level. SiPS 2022: 1-6 - 2021
- [c64]Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Jérémie Crenne, Philippe Coussy:
Extended RISC-V hardware architecture for future digital communication systems. 5GWF 2021: 224-229 - [c63]Camille Monière
Time sliding window for the detection of CCSK frames. SiPS 2021: 99-104 - 2020
- [j30]Bertrand Le Gal
Low-latency and high-throughput software turbo decoders on multi-core architectures. Ann. des Télécommunications 75(1-2): 27-42 (2020) - [j29]Yann Delomier, Bertrand Le Gal
Model-based Design of Hardware SC Polar Decoders for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 13(2): 10:1-10:27 (2020) - [j28]Bertrand Le Gal
High-Throughput FFT-SPA Decoder Implementation for Non-Binary LDPC Codes on x86 Multicore Processors. J. Signal Process. Syst. 92(1): 37-53 (2020) - [j27]Yann Delomier, Bertrand Le Gal
Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices. J. Signal Process. Syst. 92(7): 727-745 (2020) - [c62]Vincent Pignoly, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat, Lyonel Barthe:
Fair comparison of hardware and software LDPC decoder implementations for SDR space links. ICECS 2020: 1-4 - [c61]Vincent Pignoly, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat, Lyonel Barthe:
High speed LDPC decoding for optical space link. ICECS 2020: 1-4 - [c60]Bertrand Le Gal, Yann Delomier, Camille Leroux, Christophe Jégo:
Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding. SiPS 2020: 1-5
2010 – 2019
- 2019
- [j26]Adrien Cassagne
AFF3CT: A Fast Forward Error Correction Toolbox! SoftwareX 10: 100345 (2019) - [c59]Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis. SiPS 2019: 242-247 - 2018
- [j25]Bertrand Le Gal
High-performance software implementations of SCAN decoder for polar codes. Ann. des Télécommunications 73(5-6): 401-412 (2018) - [j24]Imen Debbabi
Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding. J. Signal Process. Syst. 90(11): 1551-1567 (2018) - [c58]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Hardware design of Euclidean Projection modules for ADMM LDPC decoding. ICECS 2018: 73-76 - [c57]Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
From multicore LDPC decoder implementations to FPGA decoder architectures: a case study. ICECS 2018: 89-92 - [c56]Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis. ICECS 2018: 661-664 - [c55]Safouane Noubir, Yannick Bornat, Bertrand Le Gal:
A scalable and efficient digital signal processing system for real time biological spike detection. ICECS 2018: 697-700 - [c54]Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
Model-based Design of Efficient LDPC Decoder Architectures. ISTC 2018: 1-5 - [c53]Vincent Pignoly, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat:
High data rate and flexible hardware QC-LDPC decoder for satellite optical communications. ISTC 2018: 1-5 - [c52]Imen Debbabi, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
ADMM hardware decoder for regular LDPC codes using a NISC-based architecture. WCNC 2018: 1-6 - [c51]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes. WCNC 2018: 1-6 - 2017
- [c50]Hayfa Ben Thameur, Nadia Khouja, Fethi Tlili, Bertrand Le Gal, Christophe Jégo:
An LP-based algorithm for decoding terminated LDPC convolutional codes. IINTEC 2017: 95-100 - [c49]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures. ISCC 2017: 898-905 - [c48]Bertrand Le Gal, Christophe Jégo:
Low-latency software LDPC decoders for x86 multi-core devices. SiPS 2017: 1-6 - [c47]Bertrand Le Gal, Camille Leroux, Christophe Jégo:
Successive cancellation decoder for very long polar codes. SiPS 2017: 1-6 - [c46]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Reduced complexity ADMM-based schedules for LP decoding of LDPC convolutional codes. SiPS 2017: 1-6 - [c45]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes. SoftCOM 2017: 1-5 - 2016
- [j23]Imen Debbabi
Fast Converging ADMM-Penalized Algorithm for LDPC Decoding. IEEE Commun. Lett. 20(4): 648-651 (2016) - [j22]Bertrand Le Gal
High-Throughput Multi-Core LDPC Decoders Based on x86 Processor. IEEE Trans. Parallel Distributed Syst. 27(5): 1373-1386 (2016) - [j21]Bertrand Le Gal, Yérom-David Bromberg, Laurent Réveillère, Jigar Solanki:
A Flexible SoC and Its Methodology for Parser-Based Applications. ACM Trans. Reconfigurable Technol. Syst. 10(1): 4:1-4:23 (2016) - [j20]Thibaud Tonnellier
Lowering the Error Floor of Turbo Codes With CRC Verification. IEEE Wirel. Commun. Lett. 5(4): 404-407 (2016) - [j19]Imen Debbabi
Real Time LP Decoding of LDPC Codes for High Correction Performance Applications. IEEE Wirel. Commun. Lett. 5(6): 676-679 (2016) - [c44]Thibaud Tonnellier
Hardware architecture for lowering the error floor of LTE turbo codes. DASIP 2016: 107-112 - [c43]Adrien Cassagne
Energy consumption analysis of software polar decoders on low power processors. EUSIPCO 2016: 642-646 - [c42]Imen Debbabi, Nadia Khouja, Fethi Tlili, Bertrand Le Gal, Christophe Jégo:
Multicore implementation of LDPC decoders based on ADMM algorithm. ICASSP 2016: 971-975 - [c41]Bertrand Le Gal, Camille Leroux, Christophe Jégo:
Memory reduction techniques for successive cancellation decoding of polar codes. ICASSP 2016: 986-990 - [c40]Bertrand Le Gal, Camille Leroux, Christophe Jégo:
A scalable 3-phase polar decoder. ISCAS 2016: 417-420 - [c39]Imen Debbabi, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Comparison of different schedulings for the ADMM based LDPC decoding. ISTC 2016: 51-55 - [c38]Adrien Cassagne
Beyond Gbps Turbo decoder on multi-core CPUs. ISTC 2016: 136-140 - [c37]Thibaud Tonnellier
Lowering the error floor of double-binary turbo codes: The flip and check algorithm. ISTC 2016: 156-160 - [c36]Imen Debbabi, Nadia Khouja, Fethi Tlili, Bertrand Le Gal, Christophe Jégo:
Evaluation of the hardware complexity of the ADMM approach for LDPC decoding. WCNC 2016: 1-6 - 2015
- [j18]Bertrand Le Gal, Christophe Jégo:
High-Throughput LDPC Decoder on Low-Power Embedded Processors. IEEE Commun. Lett. 19(11): 1861-1864 (2015) - [j17]Bertrand Le Gal
Multi-Gb/s Software Decoding of Polar Codes. IEEE Trans. Signal Process. 63(2): 349-359 (2015) - [c35]Imen Debbabi, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation. ICECS 2015: 356-359 - [c34]Adrien Cassagne
An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes. LCPC 2015: 303-317 - 2014
- [j16]Bertrand Le Gal, Christophe Jégo, Jérémie Crenne:
A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices. IEEE Embed. Syst. Lett. 6(2): 29-32 (2014) - [j15]Bertrand Le Gal, Christophe Jégo:
GPU-like on-chip system for decoding LDPC codes. ACM Trans. Embed. Comput. Syst. 13(4): 95:1-95:19 (2014) - [j14]Bertrand Le Gal, Christophe Jégo, Camille Leroux:
A Flexible NISC-Based LDPC Decoder. IEEE Trans. Signal Process. 62(10): 2469-2479 (2014) - [c33]Bertrand Le Gal, Camille Leroux, Christophe Jégo:
Software polar decoder on an embedded processor. SiPS 2014: 180-185 - 2013
- [j13]Bertrand Le Gal, Christophe Jégo:
Softcore Processor Optimization According to Real-Application Requirements. IEEE Embed. Syst. Lett. 5(1): 4-7 (2013) - [j12]François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini:
Design space exploration for partially reconfigurable architectures in real-time systems. J. Syst. Archit. 59(8): 571-581 (2013) - [j11]Bertrand Le Gal, Christophe Jégo:
Méthodologie d'optimisation des processeurs embarqués. Une approche favorisant la réduction de la surface et de la consommation des processeurs embarqués. Tech. Sci. Informatiques 32(6): 725-754 (2013) - [j10]Moez Kthiri, Bertrand Le Gal, Patrice Kadionik, Ahmed Ben Atitallah
A Very High Throughput Deblocking Filter for H.264/AVC. J. Signal Process. Syst. 73(2): 189-199 (2013) - [c32]A. Aulery, Dominique Dallet, Bertrand Le Gal, Nathalie Deltimple, Didier Belot, Eric Kerherve
Study and analysis of a new implementation of a mixed-signal cartesian feedback for a low power zero-IF WCDMA transmitter. NEWCAS 2013: 1-4 - [c31]Jigar Solanki, Laurent Réveillère, Yérom-David Bromberg, Bertrand Le Gal, Tegawendé F. Bissyandé:
Improving the performance of message parsers for embedded systems. SAC 2013: 1505-1510 - 2012
- [j9]Bogdan Belean
FPGA based system for automatic cDNA microarray image processing. Comput. Medical Imaging Graph. 36(5): 419-429 (2012) - [j8]Bertrand Le Gal, Lilian Bossuet:
Automatic low-cost IP watermarking technique based on output mark insertions. Des. Autom. Embed. Syst. 16(2): 71-92 (2012) - [j7]Julien Mercadal, Laurent Réveillère, Yérom-David Bromberg, Bertrand Le Gal, Tegawendé F. Bissyandé, Jigar Solanki:
Zebra: Building Efficient Network Message Parsers for Embedded Systems. IEEE Embed. Syst. Lett. 4(3): 69-72 (2012) - [j6]Emmanuel Casseau, Bertrand Le Gal:
Design of multi-mode application-specific cores based on high-level synthesis. Integr. 45(1): 9-21 (2012) - [j5]Khaled Grati
Power Consumption Models for Decimation FIR Filters in Multistandard Receivers. VLSI Design 2012: 870546:1-870546:15 (2012) - [c30]Willy Aubry, Bertrand Le Gal, Daniel Négru, Simon Desfarges, Dominique Dallet:
A generic video adaptation FPGA implementation towards content- and context-awareness in future networks. DASIP 2012: 1-7 - [c29]Bertrand Le Gal, Christophe Jégo:
FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard. DASIP 2012: 1-2 - [c28]Willy Aubry, Daniel Négru, Bertrand Le Gal, Simon Desfarges, Dominique Dallet:
A generic video adaptation framework towards content-and context-awareness in future networks. EUSIPCO 2012: 2218-2222 - [c27]W. Sanaa, Bertrand Le Gal, Dominique Dallet, Chiheb Rebai
New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitter. NEWCAS 2012: 93-96 - [c26]Bertrand Le Gal, Christophe Jégo:
Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards. SiPS 2012: 19-24 - [c25]Willy Aubry, Daniel Négru, Bertrand Le Gal, Dominique Dallet:
Spatial downsizing impact in the transrating tradeoff for content/context awareness in media network. TEMU 2012: 158-162 - 2011
- [j4]Bertrand Le Gal, Emmanuel Casseau:
Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. EURASIP J. Adv. Signal Process. 2011 (2011) - [j3]Bertrand Le Gal, Emmanuel Casseau:
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. J. Signal Process. Syst. 62(3): 341-357 (2011) - [c24]Michael Grand, Lilian Bossuet, Bertrand Le Gal, Guy Gogniat
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios. ARC 2011: 29-40 - [c23]Aurélien Ribon, Bertrand Le Gal, Christophe Jégo, Dominique Dallet:
Assertion support in high-level synthesis design flow. FDL 2011: 1-8 - [c22]Willy Aubry, Bertrand Le Gal, Dominique Dallet, Simon Desfarges, Daniel Négru:
A system aproach for reducing power consumption of multimedia devices with a low QoE impact. ICECS 2011: 5-8 - [c21]Michael Grand, Lilian Bossuet, Guy Gogniat
A Reconfigurable Multi-core Cryptoprocessor for Multi-channel Communication Systems. IPDPS Workshops 2011: 204-211 - [c20]Bogdan Belean
FPGA technology and parallel computing towards automatic microarray image processing. TSP 2011: 607-610 - 2010
- [c19]Bertrand Le Gal, Aurélien Ribon, Lilian Bossuet, Dominique Dallet:
Area optimization of ROM-based controllers dedicated to digital signal processing applications. EUSIPCO 2010: 547-551 - [c18]Nicolas Mechouk, Dominique Dallet, Lilian Bossuet, Bertrand Le Gal:
A low-area filter bank design methodology for on-chip ADC testing. ICECS 2010: 718-721 - [c17]Bertrand Le Gal, Aurélien Ribon, Lilian Bossuet, Dominique Dallet:
Reducing and smoothing power consumption of ROM-based controller implementations. SBCCI 2010: 8-13
2000 – 2009
- 2009
- [c16]Nadia Khouja, Bertrand Le Gal, Khaled Grati, Adel Ghazel:
Experiments on designing low power decimation filter for multistandard receiver on heterogeneous targets. EUSIPCO 2009: 1284-1288 - [c15]Bertrand Le Gal, Emmanuel Casseau:
Automated multimode system design for high performance DSP applications. EUSIPCO 2009: 1289-1293 - [c14]Emmanuel Casseau, Bertrand Le Gal:
High-level synthesis for the design of FPGA-based signal processing systems. ICSAMOS 2009: 25-32 - [c13]Nadia Khouja, Khaled Grati, Adel Ghazel, Bertrand Le Gal:
Design and implementation of a reconfigurable decimation and channel selection filter for GSM and UMTS radio standards. WCNC 2009: 323-328 - 2008
- [j2]Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina:
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. Tech. Sci. Informatiques 27(9-10): 1129-1154 (2008) - [j1]Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet:
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1454-1464 (2008) - [c12]Guillaume Ferré, Bertrand Le Gal, Lilian Bossuet, Maher Jridi, Dominique Dallet, Pierre Colucci:
Orthogonal correction implementation for time interleaved analog-to-digital converters: Realtime application. EUSIPCO 2008: 1-5 - [c11]Guillaume Ferré, Maher Jridi, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet:
A new orthogonal online digital calibration for time-interleaved analog-to-digital converters. ISCAS 2008: 576-579 - 2007
- [c10]Bertrand Le Gal, Lilian Bossuet, Dominique Dallet:
Mathematical functions based watermarking for IPP. ICECS 2007: 310-313 - [c9]Bertrand Le Gal, Lilian Bossuet, Shafqat Khan, Emmanuel Casseau:
HLS design flow for the synthesis of multimode systems under multiple constraints. ICECS 2007: 314-317 - 2006
- [c8]Bertrand Le Gal, Emmanuel Casseau:
IP Generation Targeting Multiple Bit-Width Standards. ICECS 2006: 784-787 - [c7]Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau:
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. SiPS 2006: 280-285 - [c6]Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau:
Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems. SoCC 2006: 175-178 - 2005
- [c5]Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno:
Hardware Virtual Components Compliant with Communication System Standards. DSD 2005: 88-95 - [c4]Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin:
C-based rapid prototyping for digital signal processing. EUSIPCO 2005: 1-4 - [c3]Bertrand Le Gal, Emmanuel Casseau, Eric Martin:
Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. EUSIPCO 2005: 1-4 - [c2]Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin:
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. ISVLSI 2005: 268-269 - 2004
- [c1]Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin:
Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) 2004: 173-176
Coauthor Index
[j32] [c74] [c73] [c69] [c67] [c65] [j30] [j29] [j28] [j27] [c62] [c61] [c60] [j26] [c59] [j25] [j24] [c58] [c57] [c56] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [j23] [j22] [j20] [j19] [c44] [c42] [c41] [c40] [c39] [c37] [c36] [j18] [j17] [c35] [j16] [j15] [j14] [c33] [j13] [j11] [c29] [c26] [c23] [c5] [c4] [c1]
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