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CICC 2004: Orlando, FL, USA
- Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004. IEEE 2004, ISBN 0-7803-8495-4
- Hailing Wang, Gennady Gildenblat:
A robust large signal non-quasi-static MOSFET model for circuit simulation. 5-8 - Peter Bendix, Pat Rakers, P. Wagh, Laurent Lemaitre, Wladek Grabinski, Colin C. McAndrew, Xin Gu, Gennady Gildenblat:
RF distortion analysis with compact MOSFET models. 9-12 - Xuemei Xi, Jin He, Mohan V. Dunga, Chung-Hsun Lin, Babak Heydari, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu:
The next generation BSIM for sub-100nm mixed-signal circuit simulation. 13-16 - Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Kaushik Roy:
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. 17-20 - Paul Westergaard, Timothy O. Dickson, Sorin P. Voinigescu:
A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis. 23-26 - Sergey V. Rylov, Scott K. Reynolds, Daniel W. Storaska, Brian A. Floyd
, Mohit Kapur, Thomas Zwick, Sudhir M. Gowda, Michael Sorna:
10+ Gb/s 90nm CMOS serial link demo in CBGA package. 27-30 - Vishnu Balan, Joe Caroselli, Jenn-Gang Chern, Chintan Desai, Cathy Liu:
A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization. 31-34 - Jongsun Kim, Jung-Hwan Choi, Changhyun Kim, A. F. Chang, Ingrid Verbauwhede
A low power capacitive coupled bus interface based on pulsed signaling. 35-38 - James F. Buckwalter, Ali Hajimiri
A 10Gb/s data-dependent jitter equalizer. 39-42 - Gowtham Vemulapalli, Pavan Kumar Hanumolu, Un-Ku Moon:
A 0.8V accurately-tuned continuous-time filter. 45-48 - Brian Guthrie, Tony Sayers, Adrian Spencer, John B. Hughes:
A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver [mobile phone applications]. 49-52 - Young-Ho Kim, Jung-Woo Park, Mun-Yang Park, Hyun-Kyu Yu:
A 1.8V triode-type transconductor and its application to a 10MHz 3rd-order Chebyshev low pass filter. 53-56 - Pankaj Pandey, José Silva-Martínez, Xuemei Liu:
A 500 MHz OTA-C 4th order lowpass filter with class AB CMFB in 0.35 μm CMOS technology. 57-60 - William Krenik, Dennis D. Buss, Peter Rickert:
Cellular handset integration - SIP vs. SOC. 63-70 - Cynthia Trigas, Stefan Doll, Joachim Kruecken:
MRAM and microprocessor system-in-package: technology stepping stone to advanced embedded devices. 71-79 - Giuseppe Gramegna, Massimo Franciotta, Valentina Mandará, Nino G. Bellantone, Michele Vaiana, Mario Paparo, Marco Losi, Sabyasachi Das, Philip G. Mattos:
23mm2 single-chip 0.18μm CMOS GPS receiver with 28mW-4.1 mm2 radio and CPU/DSP/RAM/ROM. 81-84 - Takayuki Miyazaki, Canh Quang Tran, Hiroshi Kawaguchi
Observation of one-fifth-of-a-clock wake-up time of power-gated circuit. 87-90 - Hiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka
Frequency-hopping vernier clock generators for multiple clock domain SoCs. 91-94 - Benton H. Calhoun, Alice Wang, Anantha P. Chandrakasan:
Device sizing for minimum energy operation in subthreshold circuits. 95-98 - Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Cross talk countermeasures in inductive inter-chip wireless superconnect. 99-102 - Sam Mandegaran, Ali Hajimiri
A breakdown voltage doubler for high voltage swing drivers. 103-106 - Jaijeet Roychowdhury:
An overview of automated macromodelling techniques for mixed-signal systems. 109-116 - Ning Dong, Jaijeet Roychowdhury:
Automated extraction of broadly applicable nonlinear analog macromodels from SPICE-level descriptions. 117-120 - Xiaolue Lai, Jaijeet Roychowdhury:
Fast, accurate prediction of PLL jitter induced by power grid noise. 121-124 - Yutao Hu, Kartikeya Mayaram:
A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulation. 125-128 - Shingo Yamanouchi, Kazuaki Kunihiro, Hikaru Hida:
An efficient algorithm for simulating error vector magnitude in nonlinear OFDM amplifiers. 129-132 - Vincent W. Leung
Analysis of envelope signal injection for improvement of RF amplifier intermodulation distortion. 133-136 - Byung-Guk Kim, Lee-Sup Kim:
A 250MHz-2GHz wide range delay-locked loop. 139-142 - Abdulkerim L. Coban, Mustafa H. Koroglu, Kashif A. Ahmed:
A 2.5-3.125 Gb/s quad transceiver with second order analog DLL based CDRs. 143-146 - (Withdrawn) Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]. 147-150
- Stephen Williams, Hugh Thompson, Mike Hufford, Eric Naviasky:
An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter. 151-154 - Chih-Wei Yao, Hiep T. Pham, Alan N. Willson Jr.:
A 625 MHz to 10 GHz clock multiplier for re-transmitting 10 Gb/s serial data. 155-158 - Jonne Lindeberg, Jouko Vankka, Johan Sommarek, Kari Halonen:
A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 μm CMOS. 159-162 - Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra:
High-speed direct digital frequency synthesizers in 0.25-μm CMOS. 163-166 - Brett Forejt, Vijay Rentala, Gangadhar Burra, Jose Arteaga:
A 250 mW class D design with direct battery hookup in a 90 nm process [audio band switching amplifier]. 169-172 - Akira Yasuda, Takashi Kimura, Koichiro Ochiai, Toshihiko Hamasaki:
A class-D amplifier using a spectrum shaping technique [audio power amplifier]. 173-176 - Pascal Lo Ré, Yoshihisa Fujimoto, Hitoshi Tani, Masayuki Miyamoto:
A delta-sigma modulator for 1-bit digital switching amplifier [audio power amplifier]. 177-180 - Sotir Ouzounov, Engel Roza, Hans Hegt, Gerard van der Weide, Arthur H. M. van Roermund:
Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis. 181-184 - Douglas Mercer:
A study of error sources in current steering digital-to-analog converters. 185-190 - Ayman Shabra, Jeffrey C. Gealow
GSM DAC with new segmented mismatch shaping technique. 191-193 - Mike Tripp, T. M. Mak, Anne Meixner:
Design considerations and DFT to enable testing of digital interfaces. 197-205 - Wooyoung Choi, Bapiraju Vinnakota, Ramesh Harjani:
A digital DFT technique for verifying the static performance of A/D converters. 207-210 - Hao-Chiao Hong
Design-for-digital-testability 30 MHz second-order Σ-Δ modulator. 211-214 - John J. Pekarik, David R. Greenberg, Basanth Jagannathan, Robert A. Groves, J. R. Jones, Raminderpal Singh, Anil Chinthakindi, Xudong Wang, Matthew J. Breitwisch, Douglas D. Coolbaugh, Peter E. Cottrell, John E. Florkey, Greg G. Freeman, R. Krishnasamy:
RFCMOS technology from 0.25μm to 65nm: the state of the art. 217-224 - Satoshi Inaba, Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima, Yasunori Okayama, Takahiro Nakauchi, Kazunari Ishimaru, Hidemi Ishiuchi:
Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology. 225-228 - J. F. Buller, R. van Bentum, J. Cheek, E. Ehrichs, M. Horstmann, S. Searles:
Opportunities and challenges in asymmetric device implementation [CMOS device scaling]. 229-232 - Peter M. Zeitzoff:
MOSFET scaling trends and challenges through the end of the roadmap. 233-240 - Haolu Xie, Rouying Zhan, Haigang Feng, Guang Chen, Albert Z. Wang, R. Gafiteanu:
A 3D mixed-mode ESD protection circuit simulation-design methodology. 243-246 - Ciaran J. Brennan, Joseph N. Kozhaya, Robert A. Proctor:
Power network analysis for ESD robustness in a 90nm ASIC design system. 247-250 - Markus P. J. Mergens, John Armer, Phillip Jozwiak, Bart Keppens, Frederic De Ranter, Koen G. Verhaege, R. Kumar:
Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies. 251-254 - Clark T.-C. Nguyen:
Vibrating RF MEMS for next generation wireless applications. 257-264 - Kostas Manetakis, Darryl Jessie, Chiewcharn Narathong:
A CMOS VCO with 48% tuning range for modern broadband systems. 265-268 - Luca Romanò, Vita Minerva, Silvia Cavalieri d'Oro, Carlo Samori, Marco Politi:
5-GHz in-phase coupled oscillators with 39% tuning range. 269-272 - Toru Tanzawa, Hiroyuki Shibayama, Ryota Terauchi, Katsumi Hisano, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Toru Takayama, Kenichi Agawa, Masayuki Koizumi, Fumitoshi Hatori:
A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter. 273-276 - Yong Zhan, Ramesh Harjani, Sachin S. Sapatnekar:
On the selection of on-chip inductors for the optimal VCO design. 277-280 - Kouichi Nagano, Koji Okamoto, Akira Yamamoto, Hiroki Mouri, Akira Kawabe, Hirokuni Fujiyama, Takashi Morie, Hiroyuki Nakahira, Masahiro Kuramochi, Minoru Ochiai, Kazutoshi Aida, Youichi Ogura, Toshihiko Takahashi, Toru Kakiage, Masao Takiguchi, Takashi Yamamoto, Hiroshi Kamiyama, Yutaka Katabe:
A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel. 283-286 - Jungeun Lee, Hyunsu Chae, Hanseung Lee, Maxim Konakov, Junghyun Lee, Jeongwon Lee:
An improved architecture of the mixed mode clock/data recovery for DVD read channel. 287-290 - Soo-Hyoung Lee, Jae-Young Shin, Ho-Young Lee, Ho-Jin Park, Kristian L. Lund, Karsten Nielsen, Jae-Whui Kim:
A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture. 291-294 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A word-parallel digital associative engine with wide search range based on Manhattan distance. 295-298 - Sang Gu Kang, Doo Hyung Woo, Hee Chul Lee:
Multiple integration method for high signal-to-noise ratio readout integrated circuit [IR focal plane array applications]. 299-302 - Brian S. Leibowitz, Bernhard E. Boser, Kristofer S. J. Pister:
A 256-element CMOS imaging receiver for free-space optical communication. 303-306 - Carlo Guardiani, Nicola Dragone, Patrick McNamara:
Proactive design for manufacturing (DFM) for nanometer SoC designs. 309-316 - Aurangzeb Khan, K. Ruparel, C. Joly, V. Ghanta, Due Le, T. Nguyen, J. Yu, Steven Yang, Irfan Ahmed, N. Burnside, V. Chagarlamudi, M. Cheung, F. Chiu, Yimu Fan, David Ge, Jaspal Gill, Pokai Huang, V. Jayapal, Oanh Kim, M. Li, Helder Mak, P. McKeever, S. Nguyen, K. Rajan, S. Riley, Peter Tran, H. Truong, A. Tsou, Demin Wang, C. Yang, J. Zhang, X. Zhong:
Design and development of 130-nanometer ICs for a multi-Gigabit switching network system. 317-320 - Joseph N. Kozhaya, Luay Bakir:
An electrically robust method for placing power gating switches in voltage islands. 321-324 - Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
Differential transmission line interconnect for high speed and low power global wiring. 325-328 - Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi:
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond. 329-332 - Sherif Hammouda, Mohamed Dessouky, Mohamed Tawfik, Wael M. Badawy
Analog IP migration using design knowledge extraction. 333-336 - Kiyoo Itoh, Kenichi Osada, Takayda Kawahara:
Reviews and future prospects of low-voltage embedded RAMs. 339-344 - Ciaran J. Brennan, Steven Eustis, John Goss, A. Humphrey, Michael Ouellette, Jeremy Rowland, Michael Fragano:
BIST controlled variable sense amp timing for 90nm embedded SRAM. 345-348 - Jinuk Luke Shin, Bruce Petrick, Howard Levy, Jinseung Son, Mandeep Singh, Vikas Mathur, Jung-Cheng Yeh, Heesung Choi, Vishal Gupta, Tom Ziaja, Ana Sonia Leon:
Design and implementation of an embedded 512KB level 2 cache subsystem. 349-352 - Amit Agarwal, Bipul C. Paul, Kaushik Roy:
Process variation in nano-scale memories: failure analysis and process tolerant architecture. 353-356 - Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara:
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. 357-360 - Rony E. Amaya, Peter H. R. Popplewell, Mark Cloutier, Calvin Plett:
Analysis and measurements of EM and substrate coupling effects in common RF integrated circuits. 363-366 - Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram:
Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates. 367-370 - Jan Hvolgaard Mikkelsen, Ole K. Jensen, Torben Larsen:
Crosstalk coupling effects of CMOS co-planar spiral inductors. 371-374 - Saeed Chehrazi, Rahim Bagheri, Asad A. Abidi:
Noise in passive FET mixers: a simple physical model. 375-378 - Saman Asgaran, M. Jamal Deen
Analytical modeling of MOSFET noise parameters for analog and RF applications. 379-382 - Jim Koeppe, Ramesh Harjani:
Enhanced analytic noise model for RF CMOS design. 383-386 - Gaurab Banerjee, David T. Becher, Celia Hung, David J. Allstot, Krishnamurthy Soumyanath:
Measurement and modeling of noise parameters for desensitized low noise amplifiers. 387-390 - Mamoru Ugajin, Akihiro Yamagishi, Junichi Kodate, Mitsuru Harada, Tsuneo Tsukahara:
Design techniques for a 1-V operation Bluetooth RF transceiver. 393-400 - Alyosha C. Molnar, Benson Lu, Steven Lanzisera, Ben W. Cook, Kristofer S. J. Pister:
An ultra-low power 900 MHz RF transceiver for wireless sensor networks. 401-404 - Nikos Haralabidis, Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis:
A cost-efficient 0.18 μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications. 405-408 - Pengfei Zhang, Lawrence Der, Dawei Guo, Isaac Sever, Taoufik Bourdi, Chris Lam, Alireza Zolfaghari, Jess Chen, Douglas Gambetta, Baohong Cheng, Sujatha Gower, Siegfi Hart, Lam Huynh, Thai Nguyen, Behzad Razavi:
A CMOS direct-conversion transceiver for IEEE 802.11a/b/g WLANs. 409-412 - Mike Hensley, Carroll Speir, Russell Stop, Kevin Behel, Carl Moreland, Greg Patterson, Dan Kelly, Manish Manglani, Michael Elliott, Scott Puckett, Joe Young, Frank Murden:
A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]. 413-416 - Lorenzo Cali, Francesco Lertora, Christian Gazzina, Monica Besana, Michele Borgatti:
Platform IC with embedded via programmable logic for fast customization. 419-422 - Yajun Ran, Malgorzata Marek-Sadowska:
Designing a via-configurable regular fabric. 423-426 - Jim Brown, Reed Packer, Jagdish Prasad, Khris Kofford, Troy Dye, Bob Kirk:
Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay. 427-429 - Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan:
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. 431-434 - Andy Yan, Steven J. E. Wilton:
Sequential synthesizable embedded programmable logic cores for system-on-chip. 435-438 - Yi Han, Larry McMurchie, Carl Sechen:
A high performance CMOS programmable logic core. 439-442 - Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis:
MAX II: A low-cost, high-performance LUT-based CPLD. 443-446 - Tohru Furuyama:
Trends and challenges of large scale embedded memories. 449-456 - Tomoyuki Ishii, Taro Osabe, Toshiyuki Mine, Toshiaki Sano, Bryan Atwood, Norifumi Kameshiro, Takao Watanabe, Kazuo Yano:
SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories. 457-463 - Alan Roth, Dick Foss, Robert McKenzie, Douglas Perry:
Advanced ternary CAM circuits on 0.13 μm logic process technology. 465-468 - Hiroshi Ito, Toshimasa Namekawa:
Pure CMOS one-time programmable memory using gate-ox anti-fuse. 469-472 - Kaveh Shakeri, James D. Meindl:
Relative inductance extraction method. 481-484 - Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda:
Efficient capacitance extraction method for interconnects with dummy fills. 485-488 - Akira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera:
Performance limitation of on-chip global interconnects for high-speed signaling. 489-492 - Rong Jiang, Charlie Chung-Ping Chen:
EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents. 493-496 - Simon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Kjell O. Jeppson:
A surface potential model for predicting substrate noise coupling in integrated circuits. 497-500 - Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. 501-504 - Masud H. Chowdhury, Yehea I. Ismail:
Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs]. 505-508 - Shen Lin, Makoto Nagata
Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. 509-512 - Ki Young Nam, Sang-Min Lee, David K. Su, Bruce A. Wooley:
A 1.2-V 15-bit 2.5-MS/s oversampling ADC with reduced integrator swings. 515-518 - Hugh Thompson, Mike Hufford, William Evans, Eric Naviasky:
A low-voltage low-power sigma-delta modulator with improved performance in overload condition. 519-522 - Xuesheng Wang, Yuhua Guo, Un-Ku Moon, Gabor C. Temes:
Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs. 523-526 - Susana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos:
Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. 527-530 - Ivan John O'Connell
Efficient sampling of reference noise in a switched capacitor ΣΔ ADC. 531-534 - Jinseok Koh, Khurram Muhammad, Robert Bogdan Staszewski
A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process. 535-538 - Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer:
Design and manufacturability aspect of SOI CMOS RFICs. 541-548 - Poojan Wagh, Pallab Midya, Pat Rakers, James Caldwell, Tony Schooler:
An all-digital universal RF transmitter [CMOS RF modulator and PA]. 549-552 - Alessandro Italia, Luca La Paglia, Antonino Scuderi, Francesco Carrara, Egidio Ragonese, Giuseppe Palmisano:
A 5-GHz silicon bipolar transmitter front-end for wireless LAN applications. 553-556 - Yongwang Ding, Ramesh Harjani:
A CMOS high efficiency +22 dBm linear power amplifier. 557-560 - Abbas Komijani, Ali Hajimiri
A 24GHz, +14.5dBm fully-integrated power amplifier in 0.18 μm CMOS. 561-564 - Aristotele Hadjichristos, Joel Walukas, Nikolaus Klemmer, Wen Suter, Scott Justice, Satish Uppathil, Gary Scott:
A highly integrated quad band low EVM polar modulation transmitter for GSM/EDGE applications. 565-568 - David R. Pehlke, Aristotele Hadjichristos, Scott Justice:
High performance open-loop AM modulator designed for power control of E-GPRS polar modulated power amplifier. 569-572 - John Glossner, Kai Chirca, Michael J. Schulte, Haoran Wang, Nasir Nasimzada, David Har, Shenghong Wang, A. Joseph Hoane, Gary Nacer, Mayan Moudgill, Stamatis Vassiliadis:
Sandblaster low power DSP [parallel DSP arithmetic microarchitecture]. 575-581 - Young-Don Bae, In-Cheol Park
A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors. 583-586 - Raúl Blázquez, Puneet P. Newaskar, Fred S. Lee, Anantha P. Chandrakasan:
A baseband processor for pulsed ultra-wideband signals. 587-590 - Mehmet R. Yuce, Wentai Liu, Bhaskar Bharath, John Damiano
The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers. 591-594 - Massimo Bocchi, Claudia De Bartolomeis, Claudio Mucci, Fabio Campi, Andrea Lodi, Mario Toma, Roberto Canegallo, Roberto Guerrieri:
A XiRisc-based SoC for embedded DSP applications. 595-598 - Naoto Miyamoto, Koji Kotani, Kazuyuki Maruo, Tadahiro Ohmi:
An image recognition processor using dynamically reconfigurable ALU. 599-602 - Ranjit Gharpurey:
A broadband low-noise front-end amplifier for ultra wideband in 0.13 μm CMOS. 605-608 - Hakan Dogan, Robert G. Meyer, Ali M. Niknejad:
A DC-10GHz linear-in-dB attenuator in 0.13 μm CMOS technology. 609-612 - Giovanni Girlando, Tino Copani, Santo A. Smerzi, Giuseppe Palmisano:
A Ku-band monolithic tuner-LNB for satellite applications [low noise block down-converter]. 613-616 - Tak Shun Dickson Cheung, John R. Long, Youri Tretiakov, David L. Harame:
A 21-27GHz self-shielded 4-way power-combining PA balun. 617-620 - Peter Bode, Alexander Lampe, Markus Helfenstein, Michael Gollnick:
Improved method for measuring frequency ratios in GSM mobile phones. 621-624 - Ashoke Ravi, Ralph E. Bishop, L. Richard Carley, Krishnamurthy Soumyanath:
8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS. 625-628 - Sander L. J. Gierkink, Dandan Li, Robert C. Frye, Vito Boccuzzi:
A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver. 629-632 - Philip K. T. Mok, Ka Nang Leung
Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference. 635-642 - B. Robert Gregoire:
Optimum area allocation for minimum mismatch [IC device area optimization]. 643-646 - Seth A. Cook, Kent D. Layton, William J. Marble, Donald T. Comer, David J. Comer, Craig S. Petrie:
A programmable floating-gate voltage reference in 0.5 μm CMOS. 647-650 - Ravi Chawla, Abhishek Bandyopadhyay, Venkatesh Srinivasan, Paul E. Hasler:
A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity. 651-654 - Jonathan C. Jensen, Lawrence E. Larson:
An 8bit 3GHz Si/SiGe HBT sample-and-hold. 655-658 - Ivan Koudar:
Variable gain differential current feedback amplifier. 659-662 - Doug Josephson, Bob Gottlieb:
The crazy mixed up world of silicon debug [IC validation]. 665-670 - Erik Jan Marinissen
Infrastructure for modular SOC testing. 671-678 - Kenneth M. Brown:
System in package "the rebirth of SIP". 681-686 - Leland Spangler:
Factors influencing the design of microsystems. 687-691 - Michael A. Suster, Jun Guo, Nattapon Chaimanonart, Wen H. Ko, Darrin J. Young:
Low-noise CMOS integrated sensing electronics for capacitive MEMS strain sensors. 693-696 - Jau-Jr Lin, Xiaoling Guo, Ran Li, Jason Branch, Joe E. Brewer, Kenneth K. O:
10× improvement of power transmission over free space using integrated antennas on silicon substrates. 697-700 - Dimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri, Abdelkarim Mercha, Javier Ramos, Snezana Jenei, Lars Aspemyr, Andries J. Scholten, Piet Wambacq, Stefaan Decoutere, Stéphane Donnay, Walter De Raedt:
A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor. 701-704 - Cristiano Niclass, Alexis Rochas, Pierre-André Besse, Edoardo Charbon:
A CMOS 3D camera with millimetric depth resolution. 705-708 - Henry Y. Lui, Chong H. Lee, Rakesh H. Patel:
Power estimation and thermal budgeting methodology for FPGAs. 711-714 - Luca Ciccarelli, Andrea Lodi, Roberto Canegallo:
Low leakage circuit design for FPGAs. 715-718 - Jason Helge Anderson, Farid N. Najm:
A novel low-power FPGA routing switch. 719-722
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