default search action
Ettore Napoli
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [j46]Ettore Napoli
, Efstratios Zacharelos
Approximate Full-Adders: A Comprehensive Analysis. IEEE Access 12: 136054-136072 (2024) - [c45]Ettore Napoli, Antonio G. M. Strollo, Efstratios Zacharelos, Gennaro Di Meo:
Comprehensive Analysis of Input Order Invariant Approximate 4-2 Compressors for Binary Multipliers. ISCAS 2024: 1-5 - 2023
- [j45]Efstratios Zacharelos
Approximate squaring circuits exploiting recursive architectures. Integr. 91: 35-42 (2023) - [c44]Efstratios Zacharelos, Ciro Scognamillo, Ettore Napoli, Diego Gragnaniello
On-Chip Spike Detection and Classification using Neural Networks and Approximate Computing. BioCAS 2023: 1-5 - [c43]Gerardo Saggese, Ettore Napoli, Antonio Giuseppe Maria Strollo:
CFPM: Run-time Configurable Floating-Point Multiplier. PRIME 2023: 173-176 - 2022
- [j44]Mauro D'Arco
Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs. Sensors 22(1): 234 (2022) - [j43]Gennaro Di Meo
A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 297-308 (2022) - [j42]Antonio Giuseppe Maria Strollo
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2449-2462 (2022) - [j41]Efstratios Zacharelos
Approximate Recursive Multipliers Using Low Power Building Blocks. IEEE Trans. Emerg. Top. Comput. 10(3): 1315-1330 (2022) - [c42]Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli:
Approximate Recursive Multipliers Using Low Power Building Blocks. ARITH 2022: 67 - [c41]Italo Nunziata, Efstratios Zacharelos, Gerardo Saggese, Antonio Giuseppe Maria Strollo, Ettore Napoli:
Approximate Recursive Multipliers Using Carry Truncation and Error Compensation. PRIME 2022: 137-140 - 2021
- [j40]Ettore Napoli
Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4142-4155 (2021) - 2020
- [j39]Mauro D'Arco
Digital Circuit for Seamless Resampling ADC Output Streams. Sensors 20(6): 1619 (2020) - [j38]Ettore Napoli
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 121-134 (2020) - [j37]Antonio Giuseppe Maria Strollo
Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3021-3034 (2020) - [j36]Davide De Caro
A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications. IEEE Trans. Circuits Syst. 67-I(11): 3839-3852 (2020) - [j35]Mauro D'Arco
A Time Base Option for Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes. IEEE Trans. Instrum. Meas. 69(6): 3936-3948 (2020) - [c40]Gennaro Di Meo
Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding. ICECS 2020: 1-4 - [c39]Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo:
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. ISCAS 2020: 1 - [c38]Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra, Gennaro Di Meo:
Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j34]Gerardo Castellano, Davide De Caro, Darjn Esposito
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy. Circuits Syst. Signal Process. 38(7): 3269-3294 (2019) - [j33]Darjn Esposito
Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic. Circuits Syst. Signal Process. 38(12): 5606-5622 (2019) - [c37]Gennaro Di Meo
Variable-Rounded LMS Filter for Low-Power Applications. ApplePies 2019: 155-161 - [c36]Mauro D'Arco
Digital Circuit for the Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes. ApplePies 2019: 183-189 - 2018
- [j32]Michele De Martino
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3885-3896 (2018) - [j31]Darjn Esposito
Approximate Multipliers Based on New Approximate Compressors. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4169-4182 (2018) - [c35]Darjn Esposito, Gennaro Di Meo
Design of Low-Power Approximate LMS Filters with Precision-Scalability. ApplePies 2018: 237-243 - [c34]Darjn Esposito, Gennaro Di Meo
Quality-Scalable Approximate LMS Filter. ICECS 2018: 849-852 - [c33]Darjn Esposito, Gennaro Di Meo
On the Use of Approximate Multipliers in LMS Adaptive Filters. ISCAS 2018: 1-5 - [c32]Darjn Esposito, Gennaro Di Meo
Stall-Aware Fixed-Point Implementation of LMS Filters. PRIME 2018: 169-172 - 2017
- [j30]Davide De Caro
Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines. Circuits Syst. Signal Process. 36(4): 1341-1360 (2017) - [j29]Ettore Napoli
A SISO Register Circuit Tailored for Input Data with Low Transition Probability. IEEE Trans. Computers 66(1): 45-51 (2017) - [j28]Ettore Napoli
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1040-1050 (2017) - [j27]Davide De Caro, Ettore Napoli, Darjn Esposito
Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1187-1200 (2017) - [c31]Darjn Esposito
On the use of approximate adders in carry-save multiplier-accumulators. ISCAS 2017: 1-4 - 2016
- [c30]Valerio Marotta, Giuseppe Macera, Michael Peter Kennedy, Ettore Napoli:
Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technology. ISCAS 2016: 1650-1653 - [c29]Darjn Esposito
Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. ISCAS 2016: 1970-1973 - [c28]Ettore Napoli, Gerardo Castellano, Darjn Esposito
Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence. LASCAS 2016: 23-26 - 2015
- [j26]Mariangela Genovese, Paolo Bifulco, Davide De Caro
Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images. Integr. 49: 114-124 (2015) - [j25]Davide De Caro
A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS. IEEE J. Solid State Circuits 50(9): 2074-2089 (2015) - [j24]Darjn Esposito
Variable Latency Speculative Han-Carlson Adder. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1353-1361 (2015) - [c27]Michael Peter Kennedy, Hongjia Mo, Zhida Li, Guosheng Hu, Paolo Scognamiglio, Ettore Napoli:
The noise and spur delusion in fractional-N frequency synthesizer design. ISCAS 2015: 2577-2580 - [c26]Giorgio Lopez, Ettore Napoli, Domenico Meglio, Antonio G. M. Strollo:
An FPGA processor for real-time, fixed-point refinement of CDVS keypoints. ISCAS 2015: 2832-2835 - [c25]Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo:
FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage. LASCAS 2015: 1-4 - 2014
- [j23]Mariangela Genovese, Ettore Napoli, Davide De Caro
Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA. Integr. 47(2): 261-271 (2014) - [j22]Nicola Petra
Truncated squarer with minimum mean-square error. Microelectron. J. 45(6): 799-804 (2014) - [j21]Davide De Caro
Accurate Fixed-Point Logarithmic Converter. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 526-530 (2014) - [j20]Alessandro Cilardo, Davide De Caro
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3426-3435 (2014) - [j19]Mauro D'Arco
Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition. IEEE Trans. Instrum. Meas. 63(2): 287-294 (2014) - [j18]Mariangela Genovese, Ettore Napoli:
ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition Video. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 537-547 (2014) - [c24]Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo:
Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering. ApplePies 2014: 161-167 - [c23]Mariangela Genovese, Ettore Napoli, Nicola Petra
Hardware performance versus video quality trade-off for Gaussian mixture model based background identification systems. ICDIP 2014: 91591F - [c22]Ettore Napoli, Mauro D'Arco
FPGA based system for the generation of noise with programmable power spectrum. ISCAS 2014: 1300-1303 - [c21]Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo:
A Frequency Domain Processor for Real-Time CDVS Keypoints Extraction. SITIS 2014: 94-98 - 2013
- [j17]Mariangela Genovese
FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video. J. Electr. Comput. Eng. 2013: 129589:1-129589:8 (2013) - [j16]Mariangela Genovese
FPGA-based architecture for real time segmentation and denoising of HD video. J. Real Time Image Process. 8(4): 389-401 (2013) - [j15]Nicola Petra
NORA based TDC in 90 nm CMOS. Microelectron. J. 44(6): 489-495 (2013) - [j14]Davide De Caro
Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2375-2388 (2013) - [c20]Francesco Brandonisio, Alberto Prodomo, Michael Peter Kennedy, Ettore Napoli:
Implementation of a pulse-holding Time-to-Digital Converter on an FPGA. ECCTD 2013: 1-4 - 2012
- [j13]Michele Riccio
3D electro-thermal simulations of wide area power devices operating in avalanche condition. Microelectron. Reliab. 52(9-10): 2385-2390 (2012) - [c19]Mariangela Genovese, Ettore Napoli:
FPGA implementation of OpenCV compatible background identification circuit. CompIMAGE 2012: 75-80 - [c18]Mariangela Genovese, Ettore Napoli:
An FPGA-based Real-time Background Identification Circuit for 1080p Video. SITIS 2012: 330-335 - 2011
- [j12]Valeria Garofalo, Nicola Petra
Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error. IEEE Trans. Computers 60(9): 1366-1371 (2011) - [j11]Nicola Petra
Design of Fixed-Width Multipliers With Linear Compensation Function. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 947-960 (2011) - 2010
- [j10]Lucio Rossi, Michele Riccio
A novel UIS test system with Crowbar feedback for reduced failure energy in power devices testing. Microelectron. Reliab. 50(9-11): 1479-1483 (2010) - [j9]Michele Riccio
Analysis of large area Trench-IGBT current distribution under UIS test with the aid of lock-in thermography. Microelectron. Reliab. 50(9-11): 1725-1730 (2010) - [j8]Nicola Petra
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1312-1325 (2010) - [c17]Davide De Caro
High-speed differential resistor ladder for A/D converters. ISCAS 2010: 1723-1726 - [c16]Nicola Petra
Fixed-width CSD multipliers with minimum mean square error. ISCAS 2010: 4149-4152 - [c15]Valeria Garofalo, Marino Coppola
A novel truncated squarer with linear compensation function. ISCAS 2010: 4157-4160
2000 – 2009
- 2009
- [j7]Lucio Rossi, Michele Riccio
1300 V, 2 ms pulse inductive load switching test circuit with 20 ns selectable crowbar intervention. Microelectron. Reliab. 49(9-11): 1386-1390 (2009) - 2008
- [j6]Giovanni Breglio
Detection of localized UIS failure on IGBTs with the aid of lock-in thermography. Microelectron. Reliab. 48(8-9): 1432-1434 (2008) - [c14]Valeria Garofalo, Nicola Petra
Low error truncated multipliers for DSP applications. ICECS 2008: 29-32 - [c13]Antonio G. M. Strollo
Constrained piecewise polinomial approximation for hardware implementation of elementary functions. ICECS 2008: 698-701 - 2007
- [j5]Ettore Napoli:
Limits and application of the newly proposed deep-depletion SOI LDMOS. IET Circuits Devices Syst. 1(5): 366-371 (2007) - [j4]Giovanni Breglio
Study of a failure mechanism during UIS switching of planar PT-IGBT with current sense cell. Microelectron. Reliab. 47(9-11): 1756-1760 (2007) - [c12]Valeria Garofalo, Ettore Napoli, Nicola Petra
Code compression for ARM7 embedded systems. ECCTD 2007: 687-690 - 2005
- [j3]Antonio G. M. Strollo
A novel high-speed sense-amplifier-based flip-flop. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1266-1274 (2005) - [c11]Davide De Caro
A high-speed sense-amplifier based flip-flop. ECCTD 2005: 99-102 - 2004
- [j2]Davide De Caro
Direct digital frequency synthesizers with polynomial hyperfolding technique. IEEE Trans. Circuits Syst. II Express Briefs 51-II(7): 337-344 (2004) - [c10]Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra:
High-speed direct digital frequency synthesizers in 0.25-μm CMOS. CICC 2004: 163-166 - [c9]Antonio Giuseppe Maria Strollo, Nicola Petra, Davide De Caro, Ettore Napoli:
An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS. ESSCIRC 2004: 479-482 - 2003
- [c8]Antonio Giuseppe Maria Strollo, Davide De Caro
Direct digital frequency synthesis with dual-slope approach. ESSCIRC 2003: 397-400 - 2002
- [c7]Davide De Caro
ROM-less direct digital frequency synthesizers exploiting polynomial approximation. ICECS 2002: 481-484 - 2001
- [c6]Antonio G. M. Strollo, Ettore Napoli, Davide De Caro:
New design of squarer circuits using Booth encoding and folding techniques. ICECS 2001: 193-196 - [c5]Antonio G. M. Strollo, Ettore Napoli, Davide De Caro, Giacinto Paolo Saggese:
A reconfigurable 2D convolver for real-time SAR imaging. ICECS 2001: 741-744 - [c4]Davide De Caro, Nicola Mazzocca, Ettore Napoli, Giacinto Paolo Saggese, Antonio G. M. Strollo:
Test pattern generator for hybrid testing of combinational circuits. ICECS 2001: 745-748 - 2000
- [j1]Antonio G. M. Strollo
Analysis of power dissipation in double edge-triggered flip-flops. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 624-629 (2000) - [c3]Antonio G. M. Strollo, Ettore Napoli, Davide De Caro:
New clock-gating techniques for low-power flip-flops. ISLPED 2000: 114-119
1990 – 1999
- 1999
- [c2]Antonio G. M. Strollo, Carlo Cimino, Ettore Napoli:
Power dissipation in one-latch and two-latch double edge triggered flip-flops. ICECS 1999: 1419-1422 - [c1]Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino:
A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing. ICECS 1999: 1631-1634
Coauthor Index
Antonio G. M. Strollo
aka: Antonio Giuseppe Maria Strollo
aka: Antonio Giuseppe Maria Strollo
[j46] [c45] [j45] [c43] [j44] [j43] [j42] [j41] [c42] [c41] [j40] [j38] [j37] [j36] [c40] [c39] [c38] [j34] [j33] [c37] [j32] [j31] [c35] [c34] [c33] [c32] [j30] [j29] [j28] [j27] [c31] [c29] [c28] [j26] [j25] [j24] [c26] [c25] [j23] [j22] [j21] [j20] [c24] [c22] [c21] [j17] [j15] [j14] [j11] [j8] [c17] [c16] [c15] [c14] [c13] [c12] [j3] [c11] [j2] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [j1] [c3] [c2] [c1]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-23 21:21 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: