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Susana Patón
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2020 – today
- 2024
- [j8]Victor Medina
, Leidy Mabel Alvero-Gonzalez
Analysis of VCO-Based Continuous-Time ΣΔ ADCs Using a Subset of Phases as the Feedback Signal. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 2946-2950 (2024) - [c37]Nordin Zbida, Susana Patón, Eric Gutierrez:
A 3rd-order Noise Shaped Multistage Open-Loop Current Controlled Oscillator-based ADC with Non-Linearity Compensation. ISCAS 2024: 1-5 - [c36]Michele Noviello, Rubén Garvi, Andrés Quintero, Susana Patón:
System Analysis of Capacitance-to-Digital Converters Based on a Switched-Capacitor Feedback. MWSCAS 2024: 20-24 - 2023
- [j7]Victor Medina
A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 870-874 (2023) - [c35]Alba Páez-Montoro, Javier De Mena Pacheco, Marisa López-Vallejo, Celia López-Ongil, Susana Patón:
Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition. DCIS 2023: 1-6 - 2022
- [j6]Pablo Vera
An Analysis of Noise in Multi-Bit ΣΔ Modulators with Low-Frequency Input Signals. Sensors 22(19): 7458 (2022) - [c34]Pablo Vera, Dietmar Straeussnigg, Victor Medina, Luis Hernández, Susana Patón
Optimal reconfiguration instant in ΣΔ Modulators. ISCAS 2022: 1225-1229 - 2020
- [c33]Pablo Vera, Susana Patón
DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer. DCIS 2020: 1-6 - [c32]Fernando Cardes
Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. ISCAS 2020: 1 - [c31]Victor Medina
A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding. ISCAS 2020: 1-5 - [c30]Eric Gutierrez
Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs. MWSCAS 2020: 261-264
2010 – 2019
- 2019
- [j5]Fernando Cardes
Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 920-929 (2019) - [c29]Victor Medina
Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros. ICECS 2019: 470-473 - [c28]Pablo Vera, Susana Patón
Idle Tones Reduction in Digital Single-Bit ΣΔ Modulators. ISCAS 2019: 1-5 - 2018
- [c27]Eric Gutierrez
Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping. ICECS 2018: 805-808 - [c26]Luis Hernández, Enrique Prefasi
VCO-ADC Resolution Enhancement Using Maximum Length Sequences. ISCAS 2018: 1-4 - 2017
- [c25]Andrés Quintero
Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array. MWSCAS 2017: 683-686 - 2016
- [c24]Laura Conesa-Peraleja, Susana Patón
Signal boosting to extend the bandwidth of oversampled converters. ICECS 2016: 600-603 - 2015
- [c23]Juan A. Torreño, Susana Patón
A noise coupled ΣΔ architecture using a Non Uniform Quantizer. NORCAS 2015: 1-4 - 2014
- [c22]Enrique Prefasi
A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO. ICECS 2014: 116-119 - [c21]Laura Conesa-Peraleja, Susana Patón
Time difference amplifiers to improve the dynamic range of MASH time encoded ADCs. MWSCAS 2014: 177-180 - 2013
- [c20]Luis Hernández, Enrique Prefasi
A distortion corrected passive RC noise shaping ADC for biomedical applications. ISCAS 2013: 590-593 - [c19]Juan A. Torreño, Susana Patón
A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator. ISCAS 2013: 1043-1046 - 2012
- [c18]Luis Hernández, Enrique Prefasi
Analysis of VCO based noise shaping ADCs linearized by PWM modulation. ICECS 2012: 352-355 - 2011
- [j4]Enrique Prefasi
A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm 2 65 nm CMOS Circuit. IEEE J. Solid State Circuits 46(7): 1562-1574 (2011) - 2010
- [c17]Enrique Prefasi
A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS. ESSCIRC 2010: 430-433 - [c16]Luis Hernández, Jorge Fernández, Enrique Prefasi
A time encoded decimation filter for noise shaped power DACs. ISCAS 2010: 289-292 - [c15]Susana Patón
Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters. ISCAS 2010: 4009-4012
2000 – 2009
- 2009
- [j3]Enrique Prefasi
A 0.1 mm2, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS. IEEE J. Solid State Circuits 44(10): 2745-2754 (2009) - [j2]Luis Hernández, Enrique Prefasi
A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 16-20 (2009) - [c14]Enrique Prefasi
Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer. ICECS 2009: 37-40 - 2008
- [c13]Luis Hernández, Susana Patón
Resolution enhancement of sigma-delta modulators using a tracking digital filter. ICECS 2008: 1111-1114 - [c12]Luis Hernández, Susana Patón
An A/D converter based on pulse width modulation and the walsh-hadamard transform. ICECS 2008: 1217-1220 - 2006
- [c11]Susana Patón
Design of Cascaded Continuous-Time Sigma-Delta Modulators. ICECS 2006: 50-53 - [c10]Manuel Sanchez-Renedo, Susana Patón
A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback. ICECS 2006: 954-957 - [c9]Luis Hernández, Susana Patón, Andreas Wiesbauer:
Spectral shaping of clock jitter errors for continuous time sigma-delta modulators. ISCAS 2006 - 2005
- [c8]Luis Hernández, Enrique Prefasi
Synthesis of sigma delta modulators employing continuous time delays. ISCAS (4) 2005: 4070-4073 - 2004
- [j1]Susana Patón
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. IEEE J. Solid State Circuits 39(7): 1056-1063 (2004) - [c7]Susana Patón, Thomas Pötscher, Antonio Di Giandomenico, Klaus Kolhaupt, Luis Hernández, Andreas Wiesbauer, Martin Clara, Ramon Frutos:
Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. CICC 2004: 527-530 - [c6]Luis Hernández, Pieter Rombouts
A jitter insensitive continuous-time ΣΔ modulator using transmission lines. ICECS 2004: 109-112 - [c5]Luis Hernández, Andreas Wiesbauer, Susana Patón, Antonio Di Giandomenico:
Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction. ISCAS (1) 2004: 1072-1075 - 2003
- [c4]Antonio Di Giandomenico, Susana Patón
A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS. ESSCIRC 2003: 233-236 - [c3]Luis Hernández, Susana Patón:
Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance. ISCAS (1) 2003: 989-992 - 2002
- [c2]Luis Hernández, Susana Patón:
A superregenerative receiver for phase and frequency modulated carriers. ISCAS (3) 2002: 81-84
1990 – 1999
- 1999
- [c1]Luis Hernández, Susana Patón:
A continuous-time noise-shaping modulator for logarithmic A/D conversion. ISCAS (2) 1999: 364-367
Coauthor Index
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