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Noriyuki Miura
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2020 – today
- 2024
- [j47]Dehua Liang
, Jun Shiomi
StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. IEEE Open J. Circuits Syst. 5: 211-223 (2024) - [j46]Haruka Hirata
All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(1): 133-156 (2024) - [j45]Dehua Liang
A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits. ACM Trans. Embed. Comput. Syst. 23(6): 91:1-91:20 (2024) - [c67]Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi:
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. ASPDAC 2024: 618-624 - [c66]Itsuki Takada, Daiki Nitto, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi, Ryoichi Shinkuma:
Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring. CCNC 2024: 400-405 - 2023
- [c65]Dehua Liang
DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. ASP-DAC 2023: 416-422 - [c64]Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata:
A Triturated Sensing System. ISSCC 2023: 216-217 - [c63]Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura:
A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. ISSCC 2023: 218-219 - [i2]Haruka Hirata, Daiki Miyahara, Victor Arribas, Yang Li, Noriyuki Miura, Svetla Nikova, Kazuo Sakiyama:
All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M. IACR Cryptol. ePrint Arch. 2023: 1129 (2023) - 2022
- [j44]Dehua Liang
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. 105-D(7): 1273-1282 (2022) - [j43]Makoto Nagata
Physical Attack Protection Techniques for IC Chip Level Hardware Security. IEEE Trans. Very Large Scale Integr. Syst. 30(1): 5-14 (2022) - [c62]Dehua Liang
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. ASP-DAC 2022: 43-49 - [c61]Takuma Okada, Yoshihiro Midoh, Koji Nakamae, Noriyuki Miura:
Accurate measurement of charge density in nanoscale particles using an aperture optimization of Fourier based phase reconstruction. Computational Imaging 2022: 1-5 - 2021
- [j42]Shoei Nashimoto
Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. J. Cryptogr. Eng. 11(3): 289-298 (2021) - [j41]Ville Yli-Mäyry
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16: 1351-1364 (2021) - [c60]Annjhih Hsiao, Takao Takenouchi, Hiroaki Kikuchi, Kazuo Sakiyama, Noriyuki Miura:
More Accurate and Robust PRNU-Based Source Camera Identification with 3-Step 3-Class Approach. IWDW 2021: 87-101 - 2020
- [j40]Kazuo Sakiyama
Flush Code Eraser: Fast Attack Response Invalidating Cryptographic Sensitive Data. IEEE Embed. Syst. Lett. 12(2): 37-40 (2020) - [j39]Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. IEICE Trans. Electron. 103-C(10): 497-504 (2020) - [j38]Takuji Miki
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55(10): 2747-2755 (2020) - [j37]Rei Ueno
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69(4): 534-548 (2020) - [j36]Takuji Miki
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 14-18 (2020) - [c59]Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata:
A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack. ISCAS 2020: 1 - [c58]Tomoki Uemura, Yohei Watanabe, Yang Li, Noriyuki Miura, Mitsugu Iwamoto, Kazuo Sakiyama, Kazuo Ohta:
A Key Recovery Algorithm Using Random Key Leakage from AES Key Schedule. ISITA 2020: 382-386
2010 – 2019
- 2019
- [j35]Takuji Miki, Noriyuki Miura, Makoto Nagata
A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes. IEICE Trans. Electron. 102-C(7): 530-537 (2019) - [j34]Takeshi Sugawara
Side-channel leakage from sensor-based countermeasures against fault injection attack. Microelectron. J. 90: 63-71 (2019) - [c57]Takuji Miki, Makoto Nagata
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC 2019: 1-4 - [c56]Takuji Miki, Makoto Nagata
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC 2019: 25-28 - [c55]Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata
A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. ASHES@CCS 2019: 95-100 - [c54]Makoto Nagata
On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. CICC 2019: 1-6 - [c53]Yang Li, Ryota Hatano, Sho Tada, Kohei Matsuda, Noriyuki Miura, Takeshi Sugawara, Kazuo Sakiyama:
Side-Channel Leakage of Alarm Signal for a Bulk-Current-Based Laser Sensor. Inscrypt 2019: 346-361 - 2018
- [j33]Noriyuki Miura
Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor. IEEE J. Solid State Circuits 53(10): 2889-2897 (2018) - [j32]Kohei Matsuda
A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor. IEEE J. Solid State Circuits 53(11): 3174-3182 (2018) - [j31]Daisuke Fujimoto
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1320-1324 (2018) - [c52]Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD 2018: 508-515 - [c51]Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara
A 286F2/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack. ISSCC 2018: 352-354 - 2017
- [j30]Makoto Nagata
Protecting cryptographic integrated circuits with side-channel information. IEICE Electron. Express 14(2): 20162005 (2017) - [j29]Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. 100-C(6): 560-567 (2017) - [j28]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. J. Cryptol. 30(2): 373-391 (2017) - [c50]Wei He, Jakub Breier
An FPGA-compatible PLL-based sensor against fault injection attack. ASP-DAC 2017: 39-40 - [c49]Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. A-SSCC 2017: 25-28 - [c48]Takeshi Sugawara
Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis. FDTC 2017: 49-56 - [c47]Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata
15.8 A permanent digital archive system based on 4F2 x-point multi-layer metal nano-dot structure. ISSCC 2017: 270-271 - 2016
- [j27]Makoto Ikeda, Noriyuki Miura
Introduction to the Special Section on the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 51(10): 2207-2209 (2016) - [c46]Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata
PLL to the rescue: a novel EM fault countermeasure. DAC 2016: 90:1-90:6 - [c45]Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC 2016: 141-144 - [c44]Wei He, Jakub Breier
Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. FDTC 2016: 102-113 - [c43]Kohei Matsuda, Noriyuki Miura, Makoto Nagata
On-chip substrate-bounce monitoring for laser-fault countermeasure. AsianHOST 2016: 1-6 - [c42]Noriyuki Miura, Shivam Bhasin:
Attack sensing against EM leakage and injection. ISOCC 2016: 201-202 - 2015
- [j26]Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits 50(11): 2741-2749 (2015) - [c41]Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. ASP-DAC 2015: 26-27 - [c40]Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata
EM attack sensor: concept, circuit, and design-automation methodology. DAC 2015: 176:1-176:6 - [c39]Kohki Taniguchi, Noriyuki Miura, Taisuke Hayashi, Makoto Nagata
At-Product-Test Dedicated Adaptive supply-resonance suppression. VTS 2015: 1-6 - 2014
- [j25]Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. 97-C(4): 272-279 (2014) - [j24]Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Trans. Electron. 97-C(6): 546-556 (2014) - [j23]Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. IEEE J. Solid State Circuits 49(1): 223-231 (2014) - [c38]Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. A-SSCC 2014: 225-228 - [c37]Makoto Nagata
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. ATS 2014: 258-262 - [c36]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata
EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor. CHES 2014: 1-16 - [c35]Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata
Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST 2014: 32-37 - [c34]Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC 2014: 216-217 - [c33]Taisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. VLSI-DAT 2014: 1-4 - [c32]Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. VLSIC 2014: 1-2 - [i1]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki:
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. IACR Cryptol. ePrint Arch. 2014: 541 (2014) - 2013
- [j22]Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE J. Solid State Circuits 48(3): 790-800 (2013) - [j21]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c31]Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. ASP-DAC 2013: 91-92 - [c30]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c29]Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata
Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. EMC Compo 2013: 42-46 - [c28]Kumpei Yoshikawa, Yuji Harada, Noriyuki Miura, Noriaki Takeda, Yoshiyuki Saito, Makoto Nagata
Immunity evaluation of inverter chains against RF power on power delivery network. EMC Compo 2013: 232-237 - [c27]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c26]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - [c25]Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. ISSCC 2013: 200-201 - [c24]Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda:
A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. ISSCC 2013: 214-215 - [c23]Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
3D clock distribution using vertically/horizontally-coupled resonators. ISSCC 2013: 258-259 - 2012
- [j20]Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda:
A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 249-256 (2012) - [j19]Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda:
6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing. IEICE Trans. Electron. 95-C(4): 668-676 (2012) - [j18]Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda:
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. IEEE J. Solid State Circuits 47(10): 2484-2495 (2012) - [j17]Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. IEEE J. Solid State Circuits 47(10): 2496-2504 (2012) - [j16]Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. IEEE J. Solid State Circuits 47(11): 2643-2653 (2012) - [j15]Kiichi Niitsu
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1285-1294 (2012) - [c22]Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda:
Simultaneous data and power transmission using nested clover coils. ASP-DAC 2012: 555-556 - [c21]Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. CICC 2012: 1-4 - [c20]Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda:
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. COOL Chips 2012: 1-3 - [c19]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [c18]Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. ISSCC 2012: 52-54 - 2011
- [j14]Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda:
A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. IEEE J. Solid State Circuits 46(4): 965-973 (2011) - [j13]Yasuhiro Take, Noriyuki Miura, Tadahiro Kuroda:
A 30 Gb/s/Link 2.2 Tb/s/mm 2 Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface. IEEE J. Solid State Circuits 46(11): 2552-2559 (2011) - [c17]Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Rotary coding for power reduction and S/N improvement in inductive-coupling data communication. A-SSCC 2011: 205-208 - [c16]Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda:
6W/25mm2 inductive power transfer for non-contact wafer-level testing. ISSCC 2011: 230-232 - [c15]Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda:
A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking. ISSCC 2011: 490-492 - [c14]Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12Gb/s non-contact interface with coupled transmission lines. ISSCC 2011: 492-494 - 2010
- [j12]Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits 45(1): 134-141 (2010) - [j11]Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2269-2278 (2010) - [c13]Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda:
An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. ISSCC 2010: 436-437 - [c12]Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda:
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking. ISSCC 2010: 440-441
2000 – 2009
- 2009
- [j10]Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits 44(3): 947-955 (2009) - [c11]Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. CICC 2009: 449-452 - [c10]Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL 2009: 6-11 - [c9]Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC 2009: 244-245 - 2008
- [j9]Daisuke Mizoguchi, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Constant Magnetic Field Scaling in Inductive-Coupling Data Link. IEICE Trans. Electron. 91-C(2): 200-205 (2008) - [j8]Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits 43(1): 285-291 (2008) - [j7]Yoichi Yoshida, Noriyuki Miura, Tadahiro Kuroda:
A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array. IEEE J. Solid State Circuits 43(11): 2363-2369 (2008) - [c8]Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
An 11Gb/s Inductive-Coupling Link with Burst Transmission. ISSCC 2008: 298-299 - 2007
- [j6]Kiichi Niitsu
Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. 90-C(4): 829-835 (2007) - [j5]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits 42(1): 111-122 (2007) - [j4]Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda:
Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. IEEE J. Solid State Circuits 42(2): 410-421 (2007) - [c7]Noriyuki Miura, Tadahiro Kuroda:
A 1Tb/s 3W Inductive-Coupling Transceiver Chip. ASP-DAC 2007: 92-93 - [c6]Hiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda:
Wideband Inductive-coupling Interface for High-performance Portable System. CICC 2007: 13-20 - [c5]Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. ISSCC 2007: 358-608 - 2006
- [j3]Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda:
A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. IEICE Trans. Electron. 89-C(3): 320-326 (2006) - [j2]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda:
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. IEEE J. Solid State Circuits 41(1): 23-34 (2006) - [c4]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC 2006: 1676-1685 - [c3]Amit Kumar, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda:
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. VLSI Design 2006: 271-276 - 2005
- [j1]Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. IEEE J. Solid State Circuits 40(4): 829-837 (2005) - 2004
- [c2]Noriyuki Miura, Naoki Kato, Tadahiro Kuroda:
Practical methodology of post-layout gate sizing for 15% more power saving. ASP-DAC 2004: 434-437 - [c1]Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Cross talk countermeasures in inductive inter-chip wireless superconnect. CICC 2004: 99-102
Coauthor Index
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