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Stéphane Donnay
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2000 – 2009
- 2007
- [c38]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen
, Hugo De Man:
Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941 - [i1]Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. CoRR abs/0710.4723 (2007) - 2006
- [j22]Charlotte Soens, Geert Van der Plas
Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. IEEE J. Solid State Circuits 41(9): 2040-2051 (2006) - [j21]Kris Baert
Technologies for highly miniaturized autonomous sensor networks. Microelectron. J. 37(12): 1563-1568 (2006) - [j20]Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1146-1154 (2006) - [j19]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen
Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 296-305 (2006) - [j18]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen
SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 23-33 (2006) - [c37]Geert Van der Plas
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process. ISSCC 2006: 2310- - 2005
- [j17]Dimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri
A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. IEEE J. Solid State Circuits 40(7): 1434-1442 (2005) - [j16]Charlotte Soens, Geert Van der Plas
Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates. IEEE J. Solid State Circuits 40(7): 1472-1481 (2005) - [j15]Dimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri
Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors. IEEE J. Solid State Circuits 40(9): 1922-1931 (2005) - [j14]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas
Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 65-76 (2005) - [j13]Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx:
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(12): 2515-2525 (2005) - [j12]Jan Tubbax, Boris Come, Liesbet Van der Perre
Compensation of IQ imbalance and phase noise in OFDM systems. IEEE Trans. Wirel. Commun. 4(3): 872-877 (2005) - [c36]Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Substrate noise immune design of an LC-tank VCO using sensitivity functions. CICC 2005: 477-480 - [c35]Charlotte Soens, Geert Van der Plas
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE 2005: 270-275 - [c34]Andrew Fort, Claude Desset, Julien Ryckaert, Philippe De Doncker, Leo Van Biesen, Stéphane Donnay:
Ultra wide-band body area channel model. ICC 2005: 2840-2844 - 2004
- [j11]Jan Tubbax, Liesbet Van der Perre
Joint compensation of IQ imbalance, frequency offset and phase noise in OFDM receivers. Eur. Trans. Telecommun. 15(3): 283-292 (2004) - [j10]Mustafa Badaroglu, Geert Van der Plas
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits 39(7): 1119-1130 (2004) - [c33]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC 2004: 501-504 - [c32]Dimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri, Abdelkarim Mercha, Javier Ramos, Snezana Jenei, Lars Aspemyr, Andries J. Scholten, Piet Wambacq, Stefaan Decoutere, Stéphane Donnay, Walter De Raedt:
A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor. CICC 2004: 701-704 - [c31]Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859 - [c30]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas
Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93 - [c29]Gerd Vandersteen, Rik Pintelon
Extended Subspace Identification of Improper Linear Systems. DATE 2004: 454-459 - [c28]Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Performance degradation of an LC-tank VCO by impact of digital switching noise. ESSCIRC 2004: 119-122 - [c27]Jan Craninckx, Vincent Gravot, Stéphane Donnay:
A harmonic quadrature LO generator using a 90° delay-locked loop [zero-IF transceiver applications]. ESSCIRC 2004: 127-130 - [c26]Dimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri, Javier Ramos, Abdelkarim Mercha, Snezana Jenei, Stéphane Donnay, Stefaan Decoutere:
A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS. ESSCIRC 2004: 291-294 - [c25]Jan Tubbax, Boris Come, Liesbet Van der Perre, Stéphane Donnay, Marc Moonen, Hugo De Man:
Compensation of transmitter IQ imbalance for OFDM systems. ICASSP (2) 2004: 325-328 - 2003
- [j9]Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen
Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. IEEE J. Solid State Circuits 38(7): 1250-1260 (2003) - [j8]Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man:
An analytic Volterra-series-based model for a MEMS variable capacitor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2): 124-131 (2003) - [j7]Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay:
Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1215-1227 (2003) - [c24]Jan Craninckx, Stéphane Donnay:
4G terminals: how are we going to design them? DAC 2003: 79-84 - [c23]Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay:
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. DATE 2003: 10624-10629 - [c22]Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. DATE 2003: 10642-10649 - [c21]Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC 2003: 257-260 - [c20]Manuel Innocent, Piet Wambacq, Stéphane Donnay, Willy Sansen, Hugo De Man:
A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technology. ESSCIRC 2003: 457-460 - [c19]Jan Tubbax, Andrew Fort, Liesbet Van der Perre
Joint compensation of IQ imbalance and frequency offset in OFDM systems. GLOBECOM 2003: 2365-2369 - [c18]Jan Tubbax, Liesbet Van der Perre, Stéphane Donnay, Marc Engels:
Single-carrier communication using decision-feedback equalization for multiple antennas. ICC 2003: 2321-2325 - [c17]Jan Tubbax, Boris Come, Liesbet Van der Perre, Luc Deneire, Stéphane Donnay, Marc Engels:
Compensation of IQ imbalance in OFDM systems. ICC 2003: 3403-3407 - 2002
- [j6]Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen
Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. IEEE J. Solid State Circuits 37(8): 1065-1072 (2002) - [j5]Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. IEEE J. Solid State Circuits 37(11): 1383-1395 (2002) - [c16]Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen:
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC 2002: 399-404 - [c15]Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay:
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . DATE 2002: 352-356 - [c14]Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. DATE 2002: 586-590 - 2001
- [j4]Ralf Brederlow
A Mixed-Signal Design Roadmap. IEEE Des. Test Comput. 18(6): 34-46 (2001) - [c13]Gerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels
Efficient bit-error-rate estimation of multicarrier transceivers. DATE 2001: 164-168 - [c12]Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen
High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE 2001: 326-330 - [c11]Jan Tubbax, Boris Come, Liesbet Van der Perre, Luc Deneire, Stéphane Donnay, Marc Engels:
OFDM versus Single Carrier with Cyclic Prefix: a system-based comparison. VTC Fall 2001: 1115-1119 - 2000
- [j3]Marc van Heijningen, John Compiet, Piet Wambacq, Stéphane Donnay, Marc Engels
Analysis and experimental verification of digital substrate noise generation for epi-type substrates. IEEE J. Solid State Circuits 35(7): 1002-1008 (2000) - [j2]Stéphane Donnay, Philip Pieters, Kristof Vaesen, Wim Diels, Piet Wambacq, Walter De Raedt
Chip-package codesign of a low-power 5-GHz RF front end. Proc. IEEE 88(10): 1583-1597 (2000) - [c10]Gerd Vandersteen, Piet Wambacq, Yves Rolain, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens:
A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. DAC 2000: 440-445 - [c9]Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels
High-level simulation of substrate noise generation including power supply noise coupling. DAC 2000: 446-451 - [c8]Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. DATE 2000: 350-354
1990 – 1999
- 1999
- [c7]Piet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels
A Single-Package Solution for Wireless Transceivers. DATE 1999: 425- - [c6]Piet Wambacq, Gerd Vandersteen, Stéphane Donnay, Marc Engels, Ivo Bolsens, Erik Lauwers, Piet Vanassche, Georges G. E. Gielen
High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications. ICECS 1999: 525-528 - [c5]Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels
BANDIT: embedding analog-to-digital converters on digital telecom ASICs. ICECS 1999: 1377-1380 - 1998
- [j1]Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen:
High-Level Power Minimization of Analog Sensor Interface Architectures. Integr. Comput. Aided Eng. 5(4): 303-314 (1998) - [c4]Jan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen:
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon. DATE 1998: 716-720 - 1997
- [c3]Stéphane Donnay, Georges G. E. Gielen
High-level synthesis of analog sensor interface front-ends. ED&TC 1997: 56-60 - 1995
- [c2]Jan Crols, Stéphane Donnay, Michiel Steyaert
A high-level design and optimization tool for analog RF receiver front-ends. ICCAD 1995: 550-553 - 1994
- [c1]Stéphane Donnay, Koen Swings, Georges G. E. Gielen
A Methodology for Analog Design Automation in Mixed-Signal ASICs. EDAC-ETC-EUROASIC 1994: 530-534
Coauthor Index
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