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Jean-Loup Baer
Person information
- affiliation: University of Washington, Seattle, Washington, USA
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Books and Theses
- 1963
- [b1]Jean-Loup Baer:
Etude critique et données de compilation du langage Cobol. (Study critical and compilation data of the language COBOL). Joseph Fourier University, Grenoble, France, 1963
Journal Articles
- 1995
- [j25]Craig Anderson, Jean-Loup Baer:
Two techniques for improving performance on bus-based multiprocessors. Future Gener. Comput. Syst. 11(6): 537-551 (1995) - [j24]Tien-Fu Chen, Jean-Loup Baer:
Effective Hardware Based Data Prefetching for High-Performance Processors. IEEE Trans. Computers 44(5): 609-623 (1995) - 1994
- [j23]Sang Lyul Min, Jae H. Nam, Myung Soon Park, Jean-Loup Baer:
Cache-Based Data Distribution Constrained Scheduling. Int. J. High Speed Comput. 6(1): 139-155 (1994) - 1992
- [j22]Jonathan Bertoni, Jean-Loup Baer, Wen-Hann Wang:
Scaling shared-bus multiprocessors with multiple buses and shared caches: a performance study. Microprocess. Microsystems 16(7): 339-350 (1992) - [j21]Sang Lyul Min, Jean-Loup Baer:
Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps. IEEE Trans. Parallel Distributed Syst. 3(1): 25-44 (1992) - 1991
- [j20]Wen-Hann Wang, Jean-Loup Baer:
Efficient Trace-Driven Simulation Methods for Cache Performance Analysis. ACM Trans. Comput. Syst. 9(3): 222-241 (1991) - 1989
- [j19]Jean-Loup Baer, Wen-Hann Wang:
Multilevel Cache Hierarchies: Organizations, Protocols, and Performance. J. Parallel Distributed Comput. 6(3): 451-476 (1989) - [j18]Jean-Loup Baer, Yi-Bing Lin:
Improving Quicksort Performance with a Codewort Data Structure. IEEE Trans. Software Eng. 15(5): 622-631 (1989) - 1986
- [j17]James K. Archibald, Jean-Loup Baer:
Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model. ACM Trans. Comput. Syst. 4(4): 273-298 (1986) - 1985
- [j16]Sai Choi Kwan, Jean-Loup Baer:
The I/O Performance of Multiway Mergesort and Tag Sort. IEEE Trans. Computers 34(4): 383-387 (1985) - 1984
- [j15]Jean-Loup Baer:
Computer Architecture. Computer 17(10): 77-87 (1984) - 1983
- [j14]Jean-Loup Baer, Hung-Chang Du, Richard E. Ladner
:
Binary Search in a Multiprocessing Environment. IEEE Trans. Computers 32(7): 667-677 (1983) - 1981
- [j13]Ahmed S. Zaki, Jean-Loup Baer:
Query costs in HB(1) trees versus 2-3 trees. Int. J. Parallel Program. 10(6): 383-395 (1981) - 1979
- [j12]Jean-Loup Baer, Barbara Koyama:
On the Minimization of the Width of the Control Memory of Microprogammed Processors. IEEE Trans. Computers 28(4): 330-316 (1979) - 1977
- [j11]Jean-Loup Baer, B. Schwab:
A Comparison of Tree-Balancing Algorithms. Commun. ACM 20(5): 322-330 (1977) - [j10]Jean-Loup Baer, Carla Schlatter Ellis:
Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment. IEEE Trans. Software Eng. 3(6): 394-405 (1977) - 1976
- [j9]G. Kampen, Jean-Loup Baer:
The Formal Definition of Semantics by String Automata. Comput. Lang. 1(2): 121-138 (1976) - [j8]Jean-Loup Baer:
Multiprocessing Systems. IEEE Trans. Computers 25(12): 1271-1277 (1976) - [j7]Jean-Loup Baer, Gary R. Sager:
Dynamic Improvement of Locality in Virtual Memory Systems. IEEE Trans. Software Eng. 2(1): 54-62 (1976) - [j6]Jean-Loup Baer, Gary R. Sager:
Correction to "Dynamic Improvement of Locality in Virtual Memory Systems". IEEE Trans. Software Eng. 2(2): 137 (1976) - 1974
- [j5]Jean-Loup Baer:
Models for the design, simulation, and performance of distributed-function architecture. Computer 7(3): 25-30 (1974) - [j4]Jean-Loup Baer:
On Program Placement in a Directly Executable Hierarchy of Memories. IEEE Trans. Computers 23(8): 838-849 (1974) - 1973
- [j3]Jean-Loup Baer:
A Survey of Some Theoretical Aspects of Multiprocessing. ACM Comput. Surv. 5(1): 31-80 (1973) - 1970
- [j2]Jean-Loup Baer, Daniel P. Bovet, Gerald Estrin:
Legality and Other Properties of Graph Models of Computations. J. ACM 17(3): 543-554 (1970) - 1969
- [j1]Jean-Loup Baer, Gerald Estrin:
Bounds for Maxium Parallelism in a Bilogic Graph Model of Computations. IEEE Trans. Computers 18(11): 1012-1014 (1969)
Conference and Workshop Papers
- 2003
- [c47]Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal Sidhwaney:
Memory Hierarchy Design for a Multiprocessor Look-up Engine. IEEE PACT 2003: 206-216 - 2002
- [c46]Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero
Cost-Effective Compiler Directed Memory Prefetching and Bypassing. IEEE PACT 2002: 189-198 - 2000
- [c45]Wayne A. Wong, Jean-Loup Baer:
Modified LRU Policies for Improving Second-Level Cache Behavior. HPCA 2000: 49-60 - [c44]Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad:
Characterizing processor architectures for programmable network interfaces. ICS 2000: 54-65 - 1999
- [c43]Peter van Vleet, Eric J. Anderson, Lindsay Brown, Jean-Loup Baer, Anna R. Karlin:
Pursuing the Performance Potential of Dynamic Cache Line Sizes. ICCD 1999: 528-537 - [c42]Patrick Crowley, Jean-Loup Baer:
On the Use of Trace Sampling for Architectural Studies of Desktop Applications. SIGMETRICS 1999: 208-209 - 1998
- [c41]Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad:
Execution Characteristics of Desktop Applications on Windows NT. ISCA 1998: 27-38 - [c40]Jean-Loup Baer, Wen-Hann Wang:
Retrospective: On the Inclusion Properties for Multi-Level Cache Hierarchies. 25 Years ISCA: Retrospectives and Reprints 1998: 59-60 - [c39]Jean-Loup Baer, Wen-Hann Wang:
On the Inclusion Properties for Multi-Level Cache Hierarchies. 25 Years ISCA: Retrospectives and Reprints 1998: 345-352 - [c38]Xiaohan Qin, Jean-Loup Baer:
Optimizing Software Cache-coherent Cluster Architectures. SC 1998: 25 - 1997
- [c37]Xiaohan Qin, Jean-Loup Baer:
On the Use and Performance of Explicit Communication Primitives in Cache-Coherent Multiprocessor Systems. HPCA 1997: 182-193 - [c36]Xiaohan Qin, Jean-Loup Baer:
A Performance Evaluation of Cluster-Based Architectures. SIGMETRICS 1997: 237-247 - 1996
- [c35]Theodore H. Romer, Dennis Lee, Geoffrey M. Voelker, Alec Wolman, Wayne A. Wong, Jean-Loup Baer, Brian N. Bershad, Henry M. Levy:
The Structure and Performance of Interpreters. ASPLOS 1996: 150-159 - 1995
- [c34]Xiaohan Qin, Jean-Loup Baer:
A comparative study of conservative and optimistic trace-driven simulations. Annual Simulation Symposium 1995: 42-50 - [c33]Craig Anderson, Jean-Loup Baer:
Two Techniques for Improving Performance on Bus-Based Multiprocessors. HPCA 1995: 264-275 - [c32]Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grunwald:
Instruction Cache Fetch Policies for Speculative Execution. ISCA 1995: 357-367 - 1994
- [c31]Jean-Loup Baer, Tien-Fu Chen:
An Evaluation of Hardware and Software Data Prefetching. Applications in Parallel and Distributed Computing 1994: 257-266 - [c30]Richard N. Zucker, Jean-Loup Baer:
Software versus Hardware Coherence: Performance versus Cos. HICSS (1) 1994: 163-172 - [c29]Xiaohan Qin, Jean-Loup Baer:
A Parallel Trace-driven Simulator: Implementation and Performance. ICPP (2) 1994: 314-318 - [c28]Tien-Fu Chen, Jean-Loup Baer:
A Performance Study of Software and Hardware Data Prefetching Schemes. ISCA 1994: 223-232 - 1993
- [c27]Craig Anderson, Jean-Loup Baer:
A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors. IPPS 1993: 142-148 - 1992
- [c26]Tien-Fu Chen, Jean-Loup Baer:
Reducing Memory Latency via Non-blocking and Prefetching Caches. ASPLOS 1992: 51-61 - [c25]Richard N. Zucker, Jean-Loup Baer:
A Performance Study of Memory Consistency Models. ISCA 1992: 2-12 - 1991
- [c24]Jean-Loup Baer, Richard N. Zucker:
On Synchronization Patterns in Parallel Programs. ICPP (2) 1991: 60-67 - [c23]Jean-Loup Baer, Tien-Fu Chen:
An effective on-chip preloading scheme to reduce data access penalty. SC 1991: 176-186 - 1990
- [c22]Sang Lyul Min, Jean-Loup Baer:
A Performance Comparison of Directory-based and Timestamp-based Cache Coherence Schemes. ICPP (1) 1990: 305-311 - [c21]Sang Lyul Min, Jean-Loup Baer, Hyoung-Joo Kim:
An efficient caching support for critical sections in large-scale shared-memory multiprocessors. ICS 1990: 34-47 - [c20]Wen-Hann Wang, Jean-Loup Baer:
Efficient Trace-Driven Simulation Methods for Cache Performance Analysis. SIGMETRICS 1990: 27-36 - 1989
- [c19]Sang Lyul Min, Jean-Loup Baer:
A Timestamp-based Cache Coherence Scheme. ICPP (1) 1989: 23-32 - [c18]Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan:
Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis. ICPP (1) 1989: 41-50 - [c17]Wen-Hann Wang, Jean-Loup Baer, Henry M. Levy:
Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy. ISCA 1989: 140-148 - [c16]Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska
Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks. ISCA 1989: 158-166 - 1988
- [c15]Jean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder:
A Notation for Describing Multiple Views of VLSI Circuits. DAC 1988: 102-107 - [c14]Jean-Loup Baer, Wen-Hann Wang:
On the Inclusion Properties for Multi-Level Cache Hierarchies. ISCA 1988: 73-80 - 1987
- [c13]Jean-Loup Baer, Wen-Hann Wang:
Architectural Choices for Multi-level Cache Hierarchies. ICPP 1987: 258-261 - 1986
- [c12]Jean-Loup Baer:
Modelling Architectural Features with Petri Nets. Advances in Petri Nets 1986: 258-277 - 1985
- [c11]Sai Choi Kwan, Jean-Loup Baer, G. Zick, T. Snyder:
Parallel Tag-Distribution Sort. ICPP 1985: 854-861 - 1984
- [c10]James K. Archibald, Jean-Loup Baer:
An Economical Solution to the Cache Coherence Problem. ISCA 1984: 355-362 - 1983
- [c9]Hung-Chang Du, Jean-Loup Baer:
On the Performance of Interleaved Memories with Non-Uniform Access Probabilities. ICPP 1983: 429-436 - 1981
- [c8]Jean-Loup Baer, Georges Gardarin, Claude Girault, Gérard Roucairol:
The Two-Step Commitment Protocol: Modeling, Specification and Proof Methodology. ICSE 1981: 363-373 - 1978
- [c7]Jean-Loup Baer:
Software control and program design issues for alterable architectures. COMPSAC 1978: 769-774 - 1977
- [c6]Jean-Loup Baer, M. Fries:
On the Efficiency of Some List Marketing Algorithms. IFIP Congress 1977: 751-756 - [c5]Jean-Loup Baer, John E. Jensen:
Simulation of Large Parallel Systems: Modelling of Tasks. Performance 1977: 53-73 - 1976
- [c4]John E. Jensen, Jean-Loup Baer:
A Model of Interference in a Shared Resource Multiprocessor. ISCA 1976: 52-57 - 1975
- [c3]Jean-Loup Baer:
Weight-balanced trees. AFIPS National Computer Conference 1975: 467-472 - 1972
- [c2]Jean-Loup Baer, Robert Caughey:
Segmentation and optimization of programs from cyclic structure analysis. AFIPS Spring Joint Computing Conference 1972: 23-36 - 1968
- [c1]Jean-Loup Baer, Daniel P. Bovet:
Compilation of arithmetic expressions for parallel computations. IFIP Congress (1) 1968: 340-346
Parts in Books or Collections
- 1972
- [p1]Jean-Loup Baer, Gary R. Sager:
Measurement and Improvement of Program Behavior under Paging Systems. Statistical Computer Performance Evaluation 1972: 241-264
Editorship
- 1996
- [e3]Jean-Loup Baer:
Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996. ACM 1996, ISBN 0-89791-786-3 [contents] - 1990
- [e2]Jean-Loup Baer, Larry Snyder, James R. Goodman:
Proceedings of the 17th Annual International Symposium on Computer Architecture, Seattle, WA, USA, June 1990. ACM 1990, ISBN 0-89791-366-3 [contents] - 1983
- [e1]Harold W. Lawson Jr., Tilak Agerwala, Hans H. Heilborn, Hideo Aiso, Lars-Erik Thorelli, Jean-Loup Baer, Mario Tokoro:
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983. ACM 1983, ISBN 0-89791-101-6 [contents]
Coauthor Index
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