ISCA

The author discusses the roles of power and size in determining the speed of a computer.

Existing taxonomies of computer architecture lack the descriptive tools to deal with the large variety of existing principles, features, and mechanisms of the existing spectrum of single processor, multi processor, and multi computer architectures. ...

A conceptual framework is presented that relates various aspects of fault-tolerance in the context of system structure and architecture. Such a framework is an essential first step for the construction of a taxonomy of fault-tolerance.

A design ...

The paper reports on a design methodology and an experimental CAD system, named Caddie, based on this methodology. Caddie supports specification, analysis and synthesis of objects that can be described as communicating processes, e.g. electronic ...

In a previous paper [8], we had presented the notion of a family of languages for the multilevel design and description of computer architectures. Details of a particular language family, currently under development, was also described. One of the ...

The object of our research is the codification of programming knowledge for the synthesis of concurrent programs. We present sample rules and techniques that we show can be used to derive two concurrent algorithms: dynamic programming (for the class of ...

In recent years, many systolic algorithms have been proposed as solutions to computationally demanding problems in signal and image processing and other areas. Such algorithms exploit the regularity and parallelism of problems to achieve high ...

Highly parallel VLSI computing structures consist of many processing elements operating simultaneously. In order for such processing elements to communicate among themselves, some provision must be made for synchronization of data transfer. The simplest ...

We describe the architecture of a class of machines intended to solve computationally intensive problems much faster than can today's machines, at no increase in cost.

We have investigated the programming of the BVM for several interesting algorithms on ...

A VLSI chip for performing relational data base operations is proposed. The chip is a tree of processors (TOP), where each chip has elementary storage and processing capabilities. A relation will be stored in the lowest levels of a TOP. More precisely, ...

In several data flow architectures, “streams” are proposed as special data structures able to improve parallel execution in functional programs by providing a pipelining effect between different program parts.

This paper describes how streams are ...

This paper presents the hardware register management and instruction block control flow sequencing provided by the PDF block processing section of the Piecewise Data Flow machine, a proposed high performance computer architecture. Combined, these ...

This paper discusses the concept of the working set for data-flow machines in order to establish one of the criteria for the realization of cost effective data-flow machines. The characteristics of program execution in conventional machines and data-...

A hardware approach to the design of data driven computers using a microprogrammed processor as a building block is proposed. The data driven computer is a network of processors virtually implementing the data flow program graph. The flexibility of ...

A cache was first used in a commercial computer in 1968,¹ and researchers have spent the last 15 years analyzing caches and suggesting improvements. In designing a VLSI instruction cache for a RISC microprocessor we have uncovered four ideas potentially ...

Shared-cache memory organizations for parallel-pipelined multiple instruction stream processors avoid the cache coherence problem of private caches by sharing single copies of common blocks. A shared cache may have a higher hit ratio, but suffers ...

The importance of reducing processor-memory bandwidth is recognized in two distinct situations: single board computer systems and microprocessors of the future. Cache memory is investigated as a way to reduce the memory-processor traffic. We show that ...

Instruction caches are analyzed both theoretically and experimentally. The theoretical analysis begins with a new model for cache referencing behavior—the loop model. This model is used to study cache organizations and replacement policies. It is ...

By compiling ordinary scientific applications programs with a radical technique called trace scheduling, we are generating code for a parallel machine that will run these programs faster than an equivalent sequential machine—we expect 10 to 30 times ...

This paper describes the architecture of a dynamically microprogrammable computer with low-level parallelism, called QA-2, which is designed as a high-performance, local host computer for laboratory use. The architectural principle of the QA-2 is the ...

Many computer systems include extra bits in each word of storage to allow detection (and possibly correction) of memory failures. These same bits can be used to implement tag-checking without sacrificing their normal error-handling properties. The ...

This paper proposes a microdiagnostic procedure for efficient fault diagnosis of bit-slice processors that are formed by an array of identical bit-slice processors. A test generation procedure for testing the entire array simultaneously instead of ...

We consider in this paper the (d,k) problem for directed graphs: to maximize the number of vertices in a digraph of degree d and diameter k. For any values of d and k, we construct a graph with a number of vertices larger than (d ²-1)/d² times the (non-...

A resource allocation problem in a reconfigurable multicomputer architecture based on rectangular CC-banyan multistage interconnection network with arbitrary fanout and arbitrary number of levels is studied. Four commonly used problem structures such as ...

This paper presents the uniform theory for describing of the shuffle-exchange type permutation networks - the theory of E_k stages. The use of this new approach is demonstrated by applying it to the flip, omega, and other incomplete permutation networks ...

An analysis of the Cray-1S architecture based on dataflow graphs is presented. The approach consists of representing the components of a Cray-1S system as the nodes of a dataflow graph and the interconnections between the components as the arcs of the ...

A pipelined implementation of MIMD operation is embodied in the HEP computer. This architectural concept should be carefully evaluated now that such a computer is available commercially. This paper studies the degree of utilization of pipelines in the ...

In analyzing electronic circuits, it is usually necessary to solve simultaneous linear equations which provide with a sparse coefficient matrix. In order to treat these problems effectively, we propose a dedicated parallel machine called 'Sparse Matrix ...

A number of educational institutions of the world offer academic programs in Computer Science for undergraduate and graduate students. Many of these programs have used a medium sized to large computer system as a facility for the students. There is a ...

The architecture of the Data Flow Signal Processor (DFSP) is discussed with the emphasis on its control mechanism. It is argued that the data flow principle can be efficiently applied to block processing operations of nonrecursive DSP computations, when ...