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DATE 2001: Munich, Germany
- Wolfgang Nebel, Ahmed Jerraya:
Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001. IEEE Computer Society 2001, ISBN 0-7695-0993-2 - Pallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti:
Abstraction of word-level linear arithmetic functions from bit-level component descriptions. 4-8 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer
:
Biasing symbolic search by means of dynamic activity profiles. 9-15 - Luc Charest, Michel Reid, El Mostapha Aboulhamid, Guy Bois:
A methodology for interfacing open source systemC with a third party software. 16 - George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou:
Behavioral synthesis with systemC. 21-25 - Robert Siegmund, Dietmar Müller:
SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design. 26-33 - Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher:
Embedded tutorial: TRP: integrating embedded test and ATE. 34-37 - Peter van Staa, Thomas Beck:
Embedded tutorial: current trends in the design of automotive electronic systems. 38-39 - Ting Zhang, Luca Benini, Giovanni De Micheli:
Component selection and matching for IP-based design. 40-46 - Thilo Demmeler, Paolo Giusto:
A universal communication model for an automotive system integration platform. 47-54 - Amer Baghdadi
An efficient architecture model for systematic design of application-specific multiprocessor SoC. 55-63 - Jürgen Ruf, Dirk W. Hoffmann, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Wolfgang Müller:
The simulation semantics of systemC. 64-70 - Jianwen Zhu:
MetaRTL: raising the abstraction level of RTL design. 71-76 - Kjetil Svarstad
A model for describing communication between aggregate objects in the specification and design of embedded systems. 77-85 - Alexander Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich:
Circuit partitioning for efficient logic BIST synthesis. 86-91 - Antonis M. Paschalis
Deterministic software-based self-testing of embedded processor cores. 92-96 - Jin-Fu Li, Cheng-Wen Wu
Memory fault diagnosis by syndrome compression. 97-101 - Ismet Bayraktaroglu, Alex Orailoglu:
Diagnosis for scan-based BIST: reaching deep into the signatures. 102-111 - Jakob Axelsson:
Methods and tools for systems engineering of automotive electronic architectures. 112 - G. Hettich, Thomas Thurner:
Vehicle electric/electronic architecture - one of the most important challenges for OEM's. 112-113 - Arjun Panday, Damien Couderc, Simon Marichalar:
AIL: description of a global electronic architecture at the vehicle scale. 112 - Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton:
Using SAT for combinational equivalence checking. 114-121 - Sherief Reda, Ashraf Salem
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams. 122-126 - Yakov Novikov, Evguenii I. Goldberg:
An efficient learning procedure for multiple implication checks. 127-135 - Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, Jonas Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong:
C/C++: progress or deadlock in system-level specification. 136-137 - Erik Larsson
An integrated system-on-chip test framework. 138-144 - Anshuman Chandra, Krishnendu Chakrabarty
Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding. 145-149 - Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki:
Testing TAPed cores and wrapped cores with the same test access mechanism. 150-155 - Silvia Chiusano
On applying the set covering model to reseeding. 156-161 - Hans-Ulrich Heidbrink:
Data management: limiter or accelerator for electronic design creativity. 162-163 - Gerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels
Efficient bit-error-rate estimation of multicarrier transceivers. 164-168 - Piet Vanassche, Georges G. E. Gielen
Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model. 169-175 - Luong Nguyen, Vincent Janicot:
Simulation method to extract characteristics for digital wireless communication systems. 176-181 - Cheng-Ta Hsieh, Lung-sheng Chen, Massoud Pedram:
Microprocessor power analysis by labeled simulation. 182-189 - Anoop Iyer, Diana Marculescu:
Power aware microarchitecture resource scaling. 190-196 - Luca Benini, Giuliano Castelli, Alberto Macii
Extending lifetime of portable systems by battery scheduling. 197-203 - Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
Efficient spectral techniques for sequential ATPG. 204-208 - Fulvio Corno
On the test of microprocessor IP cores. 209-213 - Irith Pomeranz, Sudhakar M. Reddy:
Sequence reordering to improve the levels of compaction achievable by static compaction procedures. 214-218 - Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
SEU effect analysis in an open-source router via a distributed fault injection environment. 219-225 - A. Lock, Raul Camposano, Heinrich Meyr:
The programmable platform: does one size fit all? 226-227 - Minghorng Lai, D. F. Wong
Slicing tree is a complete floorplan representation. 228-232 - Chak-Chung Cheung
Further improve circuit partitioning using GBAW logic perturbation techniques. 233-239 - Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi
Clustering based fast clock scheduling for light clock-tree. 240-245 - John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken
Power-efficient layered turbo decoder processor. 246-251 - Mariagiovanna Sami, Donatella Sciuto
Exploiting data forwarding to reduce the power budget of VLIW embedded processors. 252-257 - Alexander Worm, Holger Lamm, Norbert Wehn:
Design of low-power high-speed maximum a priori decoder architectures. 258-267 - Cassondra Neau, Khurram Muhammad, Kaushik Roy:
Low complexity FIR filters using factorization of perturbed coefficients. 268-272 - Andrea Acquaviva, Luca Benini, Bruno Riccò:
An adaptive algorithm for low-power streaming multimedia processing. 273-279 - Xun Liu, Marios C. Papaefthymiou:
A static power estimation methodolodgy for IP-based design. 280-289 - Michele Favalli
Optimization of error detecting codes for the detection of crosstalk originated errors. 290-296 - Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco, Maurizio Rebaudengo
System safety through automatic high-level code transformations: an experimental evaluation. 297-301 - Michael G. Wahl, Anthony P. Ambler, Christoph Maaß, Mohammed Rahman:
From DFT to systems test - a model based cost optimization tool. 302-306 - Alexander V. Drozd, M. V. Lobachev:
Efficient on-line testing method for a floating-point adder. 307-313 - Julio Leao da Silva Jr., J. Shamberger, M. Josie Ammer, Chunlong Guo, Suet-Fei Li, Rahul C. Shah, Tim Tuan, Michael Sheets, Jan M. Rabaey, Borivoje Nikolic
Design methodology for PicoRadio networks. 314-325 - Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen
High-level simulation of substrate noise generation from large digital circuits with multiple supplies. 326-330 - Chr. Werner, Ralf Goettsche, A. Wörner, Ulrich Ramacher:
Crosstalk noise in future digital CMOS circuits. 331-335 - P. Kralicek, Werner John, Heyno Garbe
Modeling electromagnetic emission of integrated circuits for system analysis. 336-340 - Franco Fiori, Francesco Musolino:
Analysis of EME produced by a microcontroller operation. 341-347 - Rocío del Río
Top-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technology. 348-352 - Mohamed Dessouky, Andreas Kaiser
Analog design for reuse - case study: very low-voltage sigma-delta modulator. 353-360 - Friedel Gerfers, Yiannos Manoli:
A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters. 361-369 - Srinath R. Naidu
Minimizing stand-by leakage power in static CMOS circuits. 370-376 - Chih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska:
In-place delay constrained power optimization using functional symmetries. 377-382 - Lech Józwiak, Artur Chojnacki:
High-quality sub-function construction in functional decomposition based on information relationship measures. 383-390 - José Alberto Espejo, Luis Entrena
Generalized reasoning scheme for redundancy addition and removal logic optimization. 391-397 - Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski:
LPSAT: a unified approach to RTL satisfiability. 398-402 - Fabrizio Ferrandi
Functional test generation for behaviorally sequential models. 403-410 - Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman:
High quality behavioral verification using statistical stopping criteria. 411-419 - Pierre G. Paulin, Faraydon Karim, Paul Bromley:
Network processors: a perspective on market requirements, processor architectures and embedded S/W tools. 420-429 - Michael W. Beattie, Lawrence T. Pileggi:
Efficient inductance extraction via windowing. 430-436 - Qinwei Xu, Pinaki Mazumder:
Efficient and passive modeling of transmission lines by using differential quadrature method. 437-444 - Qingjian Yu, Ernest S. Kuh:
Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements. 445-450 - Tom Chen:
On the impact of on-chip inductance on signal nets under the influence of power grid noise. 451-459 - Raimund Ubar, Artur Jutman
Timing simulation of digital circuits with binary decision diagrams. 460-466 - Paulino Ruiz-de-Clavijo
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. 467-471 - Klaus Hering, Jork Löser, Jens Markwardt:
dibSIM: a parallel functional logic simulator allowing dynamic load balancing. 472-478 - Joachim Küter, Erich Barke:
Architecture driven partitioning. 479-487 - Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés:
Low-power systems on chips (SOCs). 488 - Zaid Al-Ars, Ad J. van de Goor:
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. 496-503 - Irith Pomeranz, Sudhakar M. Reddy:
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. 504-508 - Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
CMOS open defect detection by supply current test. 509 - Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham:
Full chip false timing path identification: applications to the PowerPCTM microprocessors. 514-519 - Piet Wambacq, Gerd Vandersteen, Joel R. Phillips, Jaijeet S. Roychowdhury, Wolfgang Eberle, Baolin Yang, David E. Long, Alper Demir
CAD for RF circuits. 520-529 - Pirouz Bazargan-Sabet, Fabrice Ilponse:
Modeling crosstalk noise for deep submicron verification tools. 530-534 - Youxin Gao, D. F. Wong
A graph based algorithm for optimal buffer insertion under accurate delay models. 535-539 - Probir Sarkar, Cheng-Kok Koh:
Repeater block planning under simultaneous delay and transition time constraints. 540-545 - Luca Macchiarulo, Luca Benini, Enrico Macii:
On-the-fly layout generation for PTL macrocells. 546-551 - Tatjana Serdar, Carl Sechen:
Automatic datapath tile placement and routing. 552-559 - Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
A boolean satisfiability-based incremental rerouting approach with application to FPGAs. 560-565 - Mauricio Varea, Bashir M. Al-Hashimi:
Dual transitions petri net based modelling technique for embedded systems specification. 566-571 - Radu Marculescu
Probabilistic application modeling for system-level perfromance analysis. 572-579 - Paolo Giusto, Grant Martin, Edwin A. Harcourt:
Reliable estimation of execution time of embedded software. 580-589 - Florence Azaïs, Serge Bernard
Implementation of a linear histogram BIST for ADCs. 590-595 - Sasikumar Cherubal, Abhijit Chatterjee:
Test generation based diagnosis of device parameters for analog circuits. 596-602 - Bernhard Burdiek:
Generation of optimum test stimuli for nonlinear analog circuits using nonlinear - programming and time-domain sensitivities. 603-609 - Ron Wilson:
Managing the SoC design challenge with "Soft" hardware. 610-611 - Alex Doboli:
Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints. 612-619 - Yuan Xie, Wayne H. Wolf:
Allocation and scheduling of conditional task graph in hardware/software co-synthesis. 620-625 - Sri Parameswaran
Code placement in hardware/software co-synthesis to improve performance and reduce cost. 626-632 - Bilge Saglam Akgul, Vincent John Mooney III:
System-on-a-chip processor synchronization support in hardware. 633-641 - Reiner W. Hartenstein:
A decade of reconfigurable computing: a visionary retrospective. 642-649 - Iyad Ouaiss, Ranga Vemuri
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. 650-657 - Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich:
Optimal FPGA module placement with temporal precedence constraints. 658-667 - Claudio Passerone, Yosinori Watanabe, Luciano Lavagno:
Generation of minimal size code for scheduling graphs. 668-673 - Andreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr:
Generating production quality software development tools using a machine description language. 674-678 - Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya:
Automatic generation and targeting of application specific operating systems and embedded systems software. 679-685 - Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man:
Cache conscious data layout organization for embedded multimedia applications. 686-693 - Georges G. E. Gielen:
Design challenges and emerging EDA solutions in mixed-signal IC design. 694-695 - Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto:
CPU for PlayStation 2. 696 - Anand Mandapati:
Implementation of the ATI flipper chip. 697-698 - Susumu Narita:
SH-4 RISC microprocessor for multimedia, game machine. 699-701 - Shin-ichi Minato, Shinya Ishihara:
Streaming BDD manipulation for large-scale combinatorial problems. 702-707 - Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu:
Binary decision diagram with minimum expected path length. 708-712 - Mitchell A. Thornton
Spectral decision diagrams using graph transformations. 713-719 - Ahmed Amine Jerraya, Gérard Matheron:
Electronic system design methodology: Europe's positioning. 720-721 - Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee:
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. 722-728 - Juanjo Noguera, Rosa M. Badia
A HW/SW partitioning algorithm for dynamically reconfigurable architectures. 729 - Zhining Huang, Sharad Malik
Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. 735 - Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel:
Simulation-guided property checking based on a multi-valued AR-automata. 742-748 - Jinyong Jung, Sungjoo Yoo, Kiyoung Choi:
Performance improvement of multi-processor systems cosimulation based on SW analysis. 749-753 - Gabriela Nicolescu, Sungjoo Yoo, Ahmed Amine Jerraya:
Mixed-level cosimulation for fine gradual refinement of communication in SoC design. 754-759 - Andreas Hoffmann, Tim Kogel, Heinrich Meyr:
A framework for fast hardware-software co-simulation. 760-765 - Natividad Martínez Madrid
Analog/mixed-signal IP modeling for design reuse. 766-767 - Xu Jingnan, João C. Vital, Nuno Horta
A Skill-based library for retargetable embedded analog cores. 768-769 - Marco Rona, Gunter Krampl:
Modelling SoC devices for virtual test using VHDL. 770-771 - Rafael Castro-López
Retargeting of mixed-signal blocks for SoCs. 772-775 - C. Yeung, Anssi Haverinen, Graham Matthews, Jonathan Morris, Jauher Zaidi:
Standard bus vs. bus wrapper: what is the best solution for future SoC integration? 776-777 - Peter Grun, Nikil D. Dutt
Access pattern based local memory customization for low power embedded systems. 778-784 - Jianwen Zhu:
Static memory allocation by pointer analysis and coloring. 785-790 - George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Heuristic datapath allocation for multiple wordlength systems. 791-797 - Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri
On the verification of synthesized designs using automatically generated transformational witnesses. 798 - Albert E. Casavant, Aarti Gupta
Property-specific witness graph generation for guided simulation. 799 - Vytautas Stuikys, Giedrius Ziberkas, Robertas Damasevicius
Two approaches for developing generic components in VHDL. 800 - Gordon Cichon, Winthir Brunnbauer:
Annotated data types for addressed token passing networks. 801 - Nicola Nicolici, Bashir M. Al-Hashimi:
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. 802 - Andreas Lechner, Andrew Richardson
Towards a better understanding of failure modes and test requirements of ADCs. 803 - Md. Saffat Quasem, Sandeep K. Gupta:
Exact fault simulation for systems on Silicon that protects each core's intellectual property. 804 - Rainer Dorsch, Hans-Joachim Wunderlich:
Using mission logic for embedded testing. 805 - Alex Doboli, Ranga Vemuri:
A regularity-based hierarchical symbolic analysis method for large-scale analog networks. 806 - Markus Olbrich, Achim Rein, Erich Barke:
An improved hierarchical classification algorithm for structural analysis of integrated circuits. 807 - Eike Schmidt, Gerd Jochens, Lars Kruse, Frans Theeuwen, Wolfgang Nebel:
Automatic nonlinear memory power modelling. 808 - Dongkun Shin, Jihong Kim, Naehyuck Chang:
An operation rearrangement technique for power optimization in VLIM instruction fetch. 809 - Oscar Garnica
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. 810 - C. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus:
A register-transfer-level fault simulator for permanent and transient faults in embedded processors. 811 - Guido Bertoni
Efficient finite field digital-serial multiplier architecture for cryptography applications. 812 - Chun Wong, Paul Marchal, Peng Yang, Francky Catthoor, Hugo De Man, Aggeliki S. Prayati, Nathalie Cossement, Rudy Lauwereins, Diederik Verkest:
Task concurrency management methodology summary. 813 - Franco Fiori:
Susceptibility of analog cells to substrate interference. 814 - Arie van Staveren, Chris J. M. Verhoeven:
Order determination for frequency compensation of negative-feedback systems. 815 - Erhan Yildiz, Arie van Staveren, Chris J. M. Verhoeven:
Minimizing the number of floating bias voltage sources with integer linear programming. 816 - Gregorio Cappuccino
CMOS sizing rule for high performance long interconnects. 817 - Sandeep Koranne, Om Prakash Gangwal:
On automatic analysis of geometrically proximate nets in VSLI layout. 818 - Jens Lienig, Goeran Jerke, Thorsten Adler:
AnalogRouter: a new approach of current-driven routing for analog circuits. 819 - José Manuel Moya
A hardware-software operating system for heterogeneous designs. 820 - Andrei Sergeevich Terechko, Evert-Jan D. Pol, Jos T. J. van Eijndhoven:
PRMDL: a machine description language for clustered VLIW architectures. 821 - Marco Bekooij, Loek J. M. Engels, Albert van der Werf, Natalino G. Busá:
Functional units with conditional input/output behavior in VLIW processors. 822 - Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi:
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. 823 - Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess:
Constraint satisfaction for storage files with Fifos or stacks during scheduling. 824
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