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Nicola Nicolici
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2020 – today
- 2024
- [j57]Nicola Nicolici
:
Interview With Janusz Rajski. IEEE Des. Test 41(4): 65-69 (2024) - [j56]Nicola Nicolici
Interview With Vishwani Agrawal. IEEE Des. Test 41(5): 83-86 (2024) - [j55]Trevor E. Pogue
Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators. IEEE Trans. Computers 73(2): 495-509 (2024) - [j54]Mitchell Cooke, Nicola Nicolici:
Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2060-2073 (2024) - 2023
- [j53]Nicola Nicolici
Interview With Janet Olson. IEEE Des. Test 40(1): 112-115 (2023) - [j52]Nicola Nicolici
Interview With Prof. Sung-Mo (Steve) Kang. IEEE Des. Test 40(3): 64-67 (2023) - [i1]Trevor E. Pogue, Nicola Nicolici:
Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators. CoRR abs/2311.12224 (2023) - 2020
- [j51]Trevor E. Pogue
Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 750-763 (2020)
2010 – 2019
- 2018
- [j50]Amin Vali, Nicola Nicolici
Bit-Flip Detection-Driven Selection of Trace Signals. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1076-1089 (2018) - 2017
- [j49]Pouya Taatizadeh
Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1866-1880 (2017) - [c73]Pouya Taatizadeh, Nicola Nicolici:
An automated SAT-based method for the design of on-chip bit-flip detectors. ICCAD 2017: 101-108 - [c72]Xiaobing Shi, Nicola Nicolici:
A generic embedded sequence generator for constrained-random validation with weighted distributions. IOLTS 2017: 57-62 - 2016
- [j48]Nicola Nicolici, Haralampos-G. D. Stratigopoulos:
Guest Editors' Introduction: Top Papers from the 2015 International Test Conference. IEEE Des. Test 33(6): 5-6 (2016) - [j47]Xiaobing Shi, Nicola Nicolici
Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation. IEEE Trans. Computers 65(12): 3676-3686 (2016) - [j46]Xiaobing Shi, Nicola Nicolici:
On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 1012-1025 (2016) - [j45]Pouya Taatizadeh, Nicola Nicolici:
Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2118-2130 (2016) - [c71]Amin Vali, Nicola Nicolici:
Bit-flip detection-driven selection of trace signals. ETS 2016: 1-6 - 2015
- [c70]Pouya Taatizadeh, Nicola Nicolici:
A methodology for automated design of embedded bit-flips detectors in post-silicon validation. DATE 2015: 73-78 - [c69]Jason Thong, Nicola Nicolici:
SAT Solving using FPGA-based Heterogeneous Computing. ICCAD 2015: 232-239 - [c68]Xiaobing Shi, Nicola Nicolici:
On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation. ICCAD 2015: 808-815 - [c67]Pouya Taatizadeh, Nicola Nicolici:
Emulation-based selection and assessment of assertion checkers for post-silicon validation. ICCD 2015: 46-53 - [c66]Amin Vali, Nicola Nicolici:
Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug. NATW 2015: 17-22 - 2014
- [j44]Zahra Lak, Nicola Nicolici:
A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning. IEEE Trans. Computers 63(5): 1074-1084 (2014) - [j43]Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici:
A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation. ACM Trans. Embed. Comput. Syst. 13(4): 81:1-81:23 (2014) - [c65]Xiaobing Shi, Nicola Nicolici:
On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli. ATS 2014: 107-112 - [c64]Xiaobing Shi, Nicola Nicolici:
On-chip constrained random stimuli generation for post-silicon validation using compact masks. ITC 2014: 1-10 - 2013
- [j42]Phillip Kinsman, Nicola Nicolici:
NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging. IEEE Trans. Computers 62(3): 524-535 (2013) - [c63]Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici:
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. DAC 2013: 121:1-121:6 - [c62]Jason Thong, Nicola Nicolici:
FPGA acceleration of enhanced boolean constraint propagation for SAT solvers. ICCAD 2013: 234-241 - 2012
- [j41]Ho Fai Ko, Nicola Nicolici:
Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. IEEE Trans. Computers 61(11): 1563-1575 (2012) - [j40]Zahra Lak, Nicola Nicolici:
On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1845-1856 (2012) - [j39]Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici:
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1118-1131 (2012) - [c61]Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita:
Automated data analysis techniques for a modern silicon debug environment. ASP-DAC 2012: 298-303 - [c60]Nicola Nicolici:
On-chip stimuli generation for post-silicon validation. HLDVT 2012: 108-109 - [c59]Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici:
In-system constrained-random stimuli generation for post-silicon validation. ITC 2012: 1-10 - 2011
- [j38]George A. Constantinides, Nicola Nicolici:
Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. IEEE Des. Test Comput. 28(4): 6-7 (2011) - [j37]George A. Constantinides, Adam B. Kinsman, Nicola Nicolici:
Numerical Data Representations for FPGA-Based Scientific Computing. IEEE Des. Test Comput. 28(4): 8-17 (2011) - [j36]Adam B. Kinsman, Nicola Nicolici:
Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses. IEEE Trans. Computers 60(4): 498-507 (2011) - [j35]Ehab Anis Daoud, Nicola Nicolici:
On Using Lossy Compression for Repeatable Experiments during Silicon Debug. IEEE Trans. Computers 60(7): 937-950 (2011) - [j34]Adam B. Kinsman, Nicola Nicolici:
Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types. IEEE Trans. Computers 60(11): 1652-1663 (2011) - [j33]Adam B. Kinsman, Nicola Nicolici:
Automated Range and Precision Bit-Width Allocation for Iterative Computations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1265-1278 (2011) - [j32]Jason Thong, Nicola Nicolici:
An Optimal and Practical Approach to Single Constant Multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1373-1386 (2011) - [j31]Adam B. Kinsman, Nicola Nicolici:
A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 499-503 (2011) - [j30]Ehab Anis Daoud, Nicola Nicolici:
Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 559-570 (2011) - [j29]Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Design-for-Debug Architecture for Distributed Embedded Logic Analysis. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1380-1393 (2011) - [c58]Phillip Kinsman, Nicola Nicolici:
Dynamic binary translation to a reconfigurable target for on-the-fly acceleration. DAC 2011: 286-287 - [c57]Zahra Lak, Nicola Nicolici:
A New Algorithm for Post-Silicon Clock Measurement and Tuning. DFT 2011: 53-59 - [c56]Zahra Lak, Nicola Nicolici:
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation. ICCAD 2011: 434-441 - 2010
- [j28]Adam B. Kinsman, Nicola Nicolici:
Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 405-413 (2010) - [j27]Ramin Mafi
A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies. IEEE Trans. Haptics 3(3): 211-223 (2010) - [j26]Adam B. Kinsman, Nicola Nicolici:
Time-Multiplexed Compressed Test of SOC Designs. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1159-1172 (2010) - [c55]Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici:
Post-silicon validation opportunities, challenges and recent advances. DAC 2010: 12-17 - [c54]Adam B. Kinsman, Nicola Nicolici:
Robust design methods for hardware accelerators for iterative algorithms in scientific computing. DAC 2010: 254-257 - [c53]Kaveh Elizeh, Nicola Nicolici:
Embedded memory binding in FPGAs. DAC 2010: 457-462 - [c52]Jason Thong, Nicola Nicolici:
A novel optimal single constant multiplication algorithm. DAC 2010: 613-616 - [c51]Ho Fai Ko, Nicola Nicolici:
Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. ETS 2010: 62-67 - [c50]Behzad Mahdavikhah, Ramin Mafi
Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. FPGA 2010: 189-198 - [c49]Jason Thong, Nicola Nicolici:
Combined optimal and heuristic approaches for multiple constant multiplication. ICCD 2010: 266-273 - [c48]Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour:
Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED 2010: 675-682 - [c47]Ho Fai Ko, Nicola Nicolici:
Automated trace signals selection using the RTL descriptions. ITC 2010: 144-153 - [c46]Nicola Nicolici:
On improving real-time observability for in-system post-silicon debug. LATW 2010: 1
2000 – 2009
- 2009
- [j25]Ho Fai Ko, Nicola Nicolici:
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 285-297 (2009) - [j24]Ehab Anis Daoud, Nicola Nicolici:
Real-Time Lossless Compression for Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1387-1400 (2009) - [j23]Jason Thong, Nicola Nicolici:
Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1353-1357 (2009) - [c45]Brian C. Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic
A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. CICC 2009: 499-502 - [c44]Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris:
Automated data analysis solutions to silicon debug. DATE 2009: 982-987 - [c43]Adam B. Kinsman, Nicola Nicolici:
Finite Precision bit-width allocation using SAT-Modulo Theory. DATE 2009: 1106-1111 - [c42]Ho Fai Ko, Nicola Nicolici:
Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. ETS 2009: 17-22 - [c41]Nicola Nicolici, Ho Fai Ko:
Design-for-debug for post-silicon validation: Can high-level descriptions help? HLDVT 2009: 172-175 - [c40]Adam B. Kinsman, Nicola Nicolici:
Computational bit-width allocation for operations in vector calculus. ICCD 2009: 433-438 - 2008
- [j22]Nicola Nicolici, Patrick Girard:
Guest Editorial. J. Electron. Test. 24(4): 325-326 (2008) - [j21]Ho Fai Ko, Nicola Nicolici:
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electron. Test. 24(4): 393-403 (2008) - [j20]Ho Fai Ko, Nicola Nicolici:
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2092-2097 (2008) - [c39]Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen:
Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008 - [c38]Ho Fai Ko, Nicola Nicolici:
On Automated Trigger Event Generation in Post-Silicon Validation. DATE 2008: 256-259 - [c37]Ho Fai Ko, Nicola Nicolici:
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. DATE 2008: 1298-1303 - [c36]Ehab Anis Daoud, Nicola Nicolici:
On Bypassing Blocking Bugs during Post-Silicon Validation. ETS 2008: 69-74 - [c35]Ramin Mafi, Shahin Sirouspour, Brian Moody, Behzad Mahdavikhah, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici, Mahyar Fotoohi, D. Madill:
Hardware-based parallel computing for real-time haptic rendering of deformable objects. IROS 2008: 4187 - [c34]Ho Fai Ko, Nicola Nicolici:
A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. ISQED 2008: 649-654 - [c33]Adam B. Kinsman, Nicola Nicolici:
Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. ISQED 2008: 832-837 - [c32]Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici:
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. ITC 2008: 1-10 - 2007
- [j19]Erik Jan Marinissen
DATE 07 workshop on diagnostic services in NoCs. IEEE Des. Test Comput. 24(5): 510 (2007) - [j18]Erik Jan Marinissen
Editorial Silicon Debug and Diagnosis. IET Comput. Digit. Tech. 1(6): 659-660 (2007) - [j17]Qiang Xu
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1539-1547 (2007) - [c31]Ehab Anis, Nicola Nicolici:
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. DATE 2007: 225-230 - [c30]Nicola Nicolici, Xiaoqing Wen:
Embedded Tutorial on Low Power Test. ETS 2007: 202-210 - [c29]Ehab Anis, Nicola Nicolici:
On using lossless compression of debug data in embedded logic analysis. ITC 2007: 1-10 - 2006
- [j16]Qiang Xu
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Trans. Computers 55(4): 470-485 (2006) - [j15]Qiang Xu
Multifrequency TAM design for hierarchical SOCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 181-196 (2006) - [j14]Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici:
Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 537-548 (2006) - [c28]Ho Fai Ko, Nicola Nicolici:
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ICCD 2006: 237-242 - 2005
- [j13]Qiang Xu
Modular SOC testing with reduced wrapper count. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1894-1908 (2005) - [j12]Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Synchronization overhead in SOC compressed test. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 140-152 (2005) - [j11]Qiang Xu
Wrapper design for multifrequency IP cores. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 678-685 (2005) - [j10]Qiang Xu
Modular and rapid testing of SOCs with unwrapped logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1275-1285 (2005) - [c27]Ho Fai Ko, Qiang Xu
Register-transfer level functional scan for hierarchical designs. ASP-DAC 2005: 1172-1175 - [c26]Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty:
Multi-frequency wrapper design and optimization for embedded cores under average power constraints. DAC 2005: 123-128 - [c25]Adam B. Kinsman, Nicola Nicolici:
Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels. ETS 2005: 196-201 - [c24]Qiang Xu
On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. ITC 2005: 10 - 2004
- [j9]Nicola Nicolici, Bashir M. Al-Hashimi:
Testability Trade-Offs for BIST Data Paths. J. Electron. Test. 20(2): 169-179 (2004) - [j8]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1142-1153 (2004) - [c23]Qiang Xu, Nicola Nicolici:
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. Asian Test Symposium 2004: 2-7 - [c22]Ho Fai Ko, Nicola Nicolici:
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. Asian Test Symposium 2004: 454-459 - [c21]Qiang Xu, Nicola Nicolici:
Wrapper Design for Testing IP Cores with Multiple Clock Domains. DATE 2004: 416-421 - [c20]Ho Fai Ko, Nicola Nicolici:
Functional Illinois Scan Design at RTL. ICCD 2004: 78-81 - [c19]Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici:
Compressed Embedded Diagnosis of Logic Cores. ICCD 2004: 534-539 - [c18]Qiang Xu, Nicola Nicolici:
Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. ITC 2004: 1196-1202 - 2003
- [j7]Nicola Nicolici, Bashir M. Al-Hashimi:
Power-Conscious Test Synthesis and Scheduling. IEEE Des. Test Comput. 20(4): 48-55 (2003) - [j6]Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Variable-length input Huffman coding for system-on-a-chip test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 783-796 (2003) - [j5]Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Addressing useless test data in core-based system-on-a-chip test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1568-1580 (2003) - [c17]Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Test Data Compression: The System Integrator's Perspective. DATE 2003: 10726-10731 - [c16]Qiang Xu, Nicola Nicolici:
Delay Fault Testing of Core-Based Systems-on-a-Chi. DATE 2003: 10744-10752 - [c15]Bai Hong Fang, Nicola Nicolici:
Power-Constrained Embedded Memory BIST Architecture. DFT 2003: 451-458 - [c14]Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici:
Embedded Compact Deterministic Test for IP-Protected Cores. DFT 2003: 519- - [c13]Bai Hong Fang, Qiang Xu, Nicola Nicolici:
Hardware/Software Co-testing of Embedded Memories in Complex SOCs. ICCAD 2003: 599-606 - [c12]Qiang Xu, Nicola Nicolici:
On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. ITC 2003: 622-631 - 2002
- [j4]Nicola Nicolici, Bashir M. Al-Hashimi:
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits. IEEE Trans. Computers 51(6): 721-734 (2002) - [j3]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Power profile manipulation: a new approach for reducing test application time under power constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1217-1225 (2002) - [c11]Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. DATE 2002: 604-611 - [c10]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Scan Architecture for Shift and Capture Cycle Power Reduction. DFT 2002: 129-137 - [c9]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. ICCD 2002: 474-479 - [c8]Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. ITC 2002: 64-73 - [c7]Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. VTS 2002: 423-432 - 2001
- [c6]Nicola Nicolici, Bashir M. Al-Hashimi:
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. DATE 2001: 802 - [c5]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Power constrained test scheduling using power profile manipulation. ISCAS (5) 2001: 251-254 - [c4]Nicola Nicolici, Bashir M. Al-Hashimi:
Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. ITC 2001: 72-81 - 2000
- [j2]Nicola Nicolici, Bashir M. Al-Hashimi, Andrew D. Brown, Alan Christopher Williams:
BIST hardware synthesis for RTL data paths based on testcompatibility classes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1375-1385 (2000) - [c3]Nicola Nicolici, Bashir M. Al-Hashimi:
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. DATE 2000: 715-722 - [c2]Nicola Nicolici, Bashir M. Al-Hashimi:
Power conscious test synthesis and scheduling for BIST RTL data paths. ITC 2000: 662-671
1990 – 1999
- 1999
- [c1]Nicola Nicolici, Bashir M. Al-Hashimi:
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. DATE 1999: 289- - 1998
- [j1]Nicola Nicolici, Bashir M. Al-Hashimi:
Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing". IEEE Trans. Computers 47(12): 1426 (1998)
Coauthor Index
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