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Yue Zhang 0010
Person information
- affiliation: Beihang University, Fert Beijing Institute, Beijing, China
- affiliation (PhD 2014): University of Paris-Sud, Orsay, France
Other persons with the same name
- Yue Zhang — disambiguation page
- Yue Zhang 0001 — University of California, Irvine, CA, USA
- Yue Zhang 0002 — University of Pittsburgh, PA, USA
- Yue Zhang 0003 — University of Montreal, Bioinformatics and Genomics, Canada
- Yue Zhang 0004
— Westlake University, School of Engineering, Hangzhou, China (and 2 more)
- Yue Zhang 0005 — University of Western Ontario, London, ON, Canada
- Yue Zhang 0006 — Tsinghua University, Department of Computer Science and Technology, Beijing, China
- Yue Zhang 0007 — University of British Columbia, Vancouver, BC, Canada
- Yue Zhang 0008 — Shenyang Normal University, China
- Yue Zhang 0009
- Yue Zhang 0011
- Yue Zhang 0012 — East China Normal University, Shanghai, China
- Yue Zhang 0014
- Yue Zhang 0015
- Yue Zhang 0016
- Yue Zhang 0017
- Yue Zhang 0018 — Shanghai Jiao Tong University, School of Life Sciences and Biotechnology, Department of Bioinformatics and Biostatistics, China
- Yue Zhang 0019
- Yue Zhang 0020
- Yue Zhang 0021
- Yue Zhang 0022
- Yue Zhang 0023 — University of Toledo, College of Business and Innovation, OH, USA
- Yue Zhang 0024
- Yue Zhang 0025
- Yue Zhang 0026
- Yue Zhang 0027 — North China Electric Power University, School of Control and Computer Engineering, Beijing, China
- Yue Zhang 0028
- Yue Zhang 0029
- Yue Zhang 0030
- Yue Zhang 0031
- Yue Zhang 0032
- Yue Zhang 0033 — Southern University of Science and Technology, Department of Electrical and Electronic Engineering, Shenzhen, China (and 1 more)
- Yue Zhang 0034
- Yue Zhang 0035
- Yue Zhang 0036
- Yue Zhang 0037
- Yue Zhang 0038
- Yue Zhang 0039
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2020 – today
- 2024
- [j30]Shiyu Liu
Data-driven dynamic pricing and inventory management of an omni-channel retailer in an uncertain demand environment. Expert Syst. Appl. 244: 122948 (2024) - [j29]Haowen Zhan, Yue Zhang, Jingbo Huang, Yanjie Song, Lining Xing, Jie Wu, Zengyun Gao:
A reinforcement learning-based evolutionary algorithm for the unmanned aerial vehicles maritime search and rescue path planning problem considering multiple rescue centers. Memetic Comput. 16(3): 373-386 (2024) - [j28]Yanjie Song
Reinforcement learning-assisted evolutionary algorithm: A survey and research opportunities. Swarm Evol. Comput. 86: 101517 (2024) - [j27]Yanjie Song
Energy-Efficient Satellite Range Scheduling Using a Reinforcement Learning-Based Memetic Algorithm. IEEE Trans. Aerosp. Electron. Syst. 60(4): 4073-4087 (2024) - [j26]Yueting Li
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2405-2410 (2024) - [j25]Jinkai Wang
RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1014-1024 (2024) - [j24]Kaili Zhang, Zhongzhen Tong
A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1077-1081 (2024) - [j23]Zhipeng Guo
A Novel Search-Based Compute-in-Memory Minimum Values Generation Scheme for Low-Complexity LDPC Min-Sum Decoding. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3498-3502 (2024) - [j22]Yanjie Song
Generalized Model and Deep Reinforcement Learning-Based Evolutionary Method for Multitype Satellite Observation Scheduling. IEEE Trans. Syst. Man Cybern. Syst. 54(4): 2576-2589 (2024) - [c25]Jinkai Wang, Zekun Wang, Bojun Zhang, Zhengkun Gu, Youxiang Chen, Weisheng Zhao, Yue Zhang:
FRM-CIM: Full-Digital Recursive MAC Computing in Memory System Based on MRAM for Neural Network Applications. DAC 2024: 186:1-186:6 - 2023
- [j21]Kaili Zhang, Deming Zhang
A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3944-3953 (2023) - [c24]Jinkai Wang, Zhengkun Gu, Hongyu Wang, Zuolei Hao, Bojun Zhang, Weisheng Zhao, Yue Zhang:
TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation. DATE 2023: 1-6 - [i1]Yanjie Song, Yutong Wu, Yangyang Guo, Ran Yan
Reinforcement Learning-assisted Evolutionary Algorithm: A Survey and Research Opportunities. CoRR abs/2308.13420 (2023) - 2022
- [j20]Iosif-Angelos Fyrigos
Memristor Crossbar Arrays Performing Quantum Algorithms. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 552-563 (2022) - [j19]Jinkai Wang
Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4535-4545 (2022) - 2021
- [j18]Yue Zhang
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1193-1205 (2021) - [c23]Zuolei Hao, Yue Zhang, Jinkai Wang, Hongyu Wang, Yining Bai, Guanda Wang, Weisheng Zhao:
A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication. NANOARCH 2021: 1-6 - 2020
- [j17]Jiang Nan, Kun Zhang
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic. IEEE Access 8: 87584-87591 (2020) - [j16]Jinkai Wang, Chenyu Lian, Yining Bai
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM. IEEE Trans. Circuits Syst. 67-I(12): 4247-4258 (2020) - [c22]Zhe Huang, Yue Zhang, Kun Zhang, Zhizhong Zhang, Jinkai Wang, Youguang Zhang, Weisheng Zhao:
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device. ACM Great Lakes Symposium on VLSI 2020: 259-264 - [c21]Yining Bai, Yue Zhang, Jinkai Wang, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Kun Zhang, Weisheng Zhao:
A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM. ACM Great Lakes Symposium on VLSI 2020: 351-356 - [c20]Jinkai Wang, Yue Zhang, Chenyu Lian, Yining Bai, Zhe Huang, Guanda Wang, Kun Zhang, Youguang Zhang, Weisheng Zhao:
Efficient Time-Domain In-Memory Computing Based on TST-MRAM. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j15]Guanda Wang
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 215-225 (2019) - [c19]Yue Zhang, Jiang Nan, Guanda Wang, Xueying Zhang, Youguang Zhang, Weisheng Zhao:
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions. NANOARCH 2019: 1-2 - [c18]Guanda Wang, Yue Zhang, Zhe Huang, Jinkai Wang, Kun Zhang, Zhizhong Zhang, Youguang Zhang, Weisheng Zhao:
Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction. NANOARCH 2019: 1-6 - [c17]Jinkai Wang, Yue Zhang, Chenyu Lian, Guanda Wang, Kun Zhang, Xiulong Wu, Youguang Zhang, Weisheng Zhao:
High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM. NANOARCH 2019: 1-6 - 2018
- [c16]You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning. ACM Great Lakes Symposium on VLSI 2018: 403-408 - 2017
- [c15]Yuanzhuo Qu, Jie Han, Bruce F. Cockburn, Witold Pedrycz, Yue Zhang, Weisheng Zhao:
A true random number generator based on parallel STT-MTJs. DATE 2017: 606-609 - [c14]Guanda Wang, Yue Zhang, Zhizhong Zhang, Jiang Nan, Zhenyi Zheng, Yu Wang, Lang Zeng, Youguang Zhang, Weisheng Zhao:
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction. NANOARCH 2017: 49-54 - 2016
- [j14]You Wang, Hao Cai, Lirida A. B. Naviner
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI. Microelectron. Reliab. 64: 26-30 (2016) - [j13]Deming Zhang, Lang Zeng, Kaihua Cao, Mengxing Wang, Shouzhong Peng, Yue Zhang, Youguang Zhang, Jacques-Olivier Klein
All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron. IEEE Trans. Biomed. Circuits Syst. 10(4): 828-836 (2016) - [j12]Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 629-638 (2016) - [c13]Zhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Yichuan Shi, Youguang Zhang, Weisheng Zhao:
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy. NANOARCH 2016: 141-142 - 2015
- [j11]Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein
Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. ACM J. Emerg. Technol. Comput. Syst. 12(2): 16:1-16:42 (2015) - [j10]Mengxing Wang, Yue Zhang
Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges. Micromachines 6(8): 1023-1045 (2015) - [j9]Y. Wang, Hao Cai, Lirida A. B. Naviner
Compact thermal modeling of spin transfer torque magnetic tunnel junction. Microelectron. Reliab. 55(9-10): 1649-1653 (2015) - [j8]Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1757-1765 (2015) - [c12]Guangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, Yinan Sun, Jacques-Olivier Klein, Dafine Ravelosona, Yongpan Liu, Weisheng Zhao, Huazhong Yang:
From device to system: cross-layer design exploration of racetrack memory. DATE 2015: 1018-1023 - [c11]Yue Zhang, Chao Zhang, Jacques-Olivier Klein
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system. ISCAS 2015: 381-384 - 2014
- [j7]Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. J. Parallel Distributed Comput. 74(6): 2484-2496 (2014) - [j6]You Wang, Yue Zhang, Erya Deng, Jacques-Olivier Klein
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses. Microelectron. Reliab. 54(9-10): 1774-1778 (2014) - [j5]Weisheng Zhao, Mathieu Moreau
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 443-454 (2014) - [j4]Djaafar Chabi, Weisheng Zhao, Erya Deng, Yue Zhang, Nesrine Ben Romdhane, Jacques-Olivier Klein
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1755-1765 (2014) - [c10]Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein
An overview of spin-based integrated circuits. ASP-DAC 2014: 676-683 - [c9]Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert:
Spintronics for low-power computing. DATE 2014: 1-6 - [c8]Nesrine Ben Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires. NANOARCH 2014: 71-76 - 2013
- [j3]Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. Microelectron. Reliab. 53(9-11): 1224-1229 (2013) - [j2]Hong-Phuc Trinh, Weisheng Zhao, Jacques-Olivier Klein
Magnetic Adder Based on Racetrack Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1469-1477 (2013) - [c7]Jean-Michel Portal, Mathieu Moreau
Analytical study of complementary memristive synchronous logic gates. NANOARCH 2013: 70-75 - [c6]Djaafar Chabi, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein
Low power magnetic flip-flop based on checkpointing and self-enable mechanism. NEWCAS 2013: 1-4 - [c5]Yue Zhang, Erya Deng, Jacques-Olivier Klein
Synchronous full-adder based on complementary resistive switching memory cells. NEWCAS 2013: 1-4 - [c4]Weisheng Zhao, Jacques-Olivier Klein
Spin-electronics based logic fabrics. VLSI-SoC 2013: 174-179 - 2012
- [j1]Weisheng Zhao, Yue Zhang, Thibaut Devolder
Failure and reliability analysis of STT-MRAM. Microelectron. Reliab. 52(9-10): 1848-1852 (2012) - [c3]Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle
Crossbar architecture based on 2R complementary resistive switching memory cell. NANOARCH 2012: 85-92 - 2011
- [c2]Weisheng Zhao, Lionel Torres, Luis Vitório Cargnini
High Performance SoC Design Using Magnetic Logic and Memory. VLSI-SoC (Selected Papers) 2011: 10-33 - [c1]Weisheng Zhao, Yue Zhang, Yahya Lakys
Embedded MRAM for high-speed computing. VLSI-SoC 2011: 37-42
Coauthor Index
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