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Sylvain Clerc
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2020 – today
- 2024
- [c27]Joaquin Cornejo, Filipe Pouget, Sylvain Clerc, Tifenn Hirtzlin, Benoit Larras, Andreia Cathelin, Antoine Frappé:
Exploration of Low-Energy Floating-Point Flash Attention Mechanism for 18nm FD-SOI CMOS Integration at the Edge. MWSCAS 2024: 1056-1059 - 2023
- [c26]Soufiane Mourrane, Benoit Larras, Sylvain Clerc, Andreia Cathelin, Antoine Frappé:
A 291nW Real-Time Event-Driven Spectrogram Extraction unit in 28nm FD-SOI CMOS for Keyword Spotting Application. ESSCIRC 2023: 341-344 - [c25]Soufiane Mourrane, Benoit Larras, Sylvain Clerc, Andreia Cathelin, Antoine Frappé:
Low-Power Event-Driven Spectrogram Extractor for Multiple Keyword Spotting: A proof of concept. NEWCAS 2023: 1-5 - 2021
- [c24]Sylvain Clerc, Kedar Janardan Dhori, Robin M. Wilson, Rohit Goel, Sébastien Marchal, Franck Pourchon, Christian Dutto, Ricardo Gomez Gomez:
Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies. ESSCIRC 2021: 271-274 - 2020
- [j5]Lucien J. Breems
, Patrick Reynaert
Guest Editorial Special Section on the 45th IEEE European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 55(7): 1747-1748 (2020) - [c23]Ricardo Gomez Gomez, Edwige Bano, Andreia Cathelin, Sylvain Clerc:
A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI. VLSI Circuits 2020: 1-2 - [c22]Arnaud Verdant, William Guicquero
A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c21]Franck Arnaud, Sébastien Haendler, Sylvain Clerc, Rossella Ranica, Anna Gandolfo, Olivier Weber:
28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications. ESSCIRC 2019: 7-10 - [c20]Franck Arnaud, Sébastien Haendler, Sylvain Clerc, Rossella Ranica, Anna Gandolfo, Olivier Weber:
28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications. ESSDERC 2019: 7-10 - [c19]Ricardo Gomez Gomez, Edwige Bano, Sylvain Clerc:
Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology. ISLPED 2019: 1-6 - 2017
- [c18]Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid
A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. A-SSCC 2017: 69-72 - 2016
- [c17]Martin Cochet, Alberto Puggelli, Ben Keller, Brian Zimmer, Milovan Blagojevic, Sylvain Clerc, Philippe Roche, Jean-Luc Autran, Borivoje Nikolic
On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. A-SSCC 2016: 125-128 - [c16]Fady Abouzeid
30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. ESSCIRC 2016: 37-40 - [c15]Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche:
A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking. ISCAS 2016: 1206-1209 - 2015
- [j4]Edith Beigné
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50(1): 125-136 (2015) - [c14]Fady Abouzeid
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. ESSCIRC 2015: 108-111 - [c13]Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid
Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. IRPS 2015: 12 - [c12]Sylvain Clerc, Fady Abouzeid
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370 - [c11]Sylvain Clerc, Mehdi Saligane, Fady Abouzeid
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC 2015: 1-3 - 2014
- [j3]Fady Abouzeid
Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. IEEE J. Solid State Circuits 49(7): 1499-1505 (2014) - [j2]Jean-Luc Autran, Maximilien Glorieux, Daniela Munteanu
Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits. Microelectron. Reliab. 54(9-10): 2278-2283 (2014) - [c10]Robin Wilson, Edith Beigné
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - 2013
- [c9]Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE 2013: 613-618 - [c8]Fady Abouzeid
Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. ESSCIRC 2013: 205-208 - 2012
- [c7]Fady Abouzeid
28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder. ESSCIRC 2012: 153-156 - [c6]Sylvain Clerc, Fady Abouzeid
A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance. ESSCIRC 2012: 313-316 - [c5]Sylvain Clerc, Fady Abouzeid
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance. ICICDT 2012: 1-4 - 2011
- [j1]Fady Abouzeid
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. ACM Trans. Design Autom. Electr. Syst. 16(3): 35:1-35:17 (2011) - [c4]Sylvain Clerc, Fady Abouzeid
A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform. ICECS 2011: 117-120 - 2010
- [c3]Brice Lhomme, Yann Carminati, Bertrand Borot, Olivier Callen, Thierry Burdeau, Sylvain Clerc:
A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter. ESSCIRC 2010: 362-365
2000 – 2009
- 2009
- [c2]Fady Abouzeid
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. ISLPED 2009: 225-230 - 2008
- [c1]Sebastien Barasinski, Ludovic Camus, Sylvain Clerc:
A 45nm single power supply SRAM supporting low voltage operation down to 0.6V. ESSCIRC 2008: 502-505
Coauthor Index
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last updated on 2024-10-11 17:32 CEST by the dblp team
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