default search action
Jean-François Naviner
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2010 – 2019
- 2016
- [j18]Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner
, You Wang, Mariem Slimani, Jean-François Naviner
Efficient reliability evaluation methodologies for combinational circuits. Microelectron. Reliab. 64: 19-25 (2016) - 2015
- [j17]Hao Cai, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects. Microelectron. Reliab. 55(3-4): 645-653 (2015) - 2014
- [c32]Lirida A. B. Naviner
Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. ICICDT 2014: 1-4 - [c31]Samuel N. Pagliarini
A hybrid reliability assessment method and its support of sequential logic modelling. IOLTS 2014: 182-183 - 2013
- [j16]Samuel N. Pagliarini
SNaP: A novel hybrid method for circuit reliability assessment under multiple faults. Microelectron. Reliab. 53(9-11): 1230-1234 (2013) - [c30]Kaikai Liu, Hao Cai, Ting An, Lirida A. B. Naviner
Reliability analysis of combinational circuits with the influences of noise and single-event transients. DFTS 2013: 218-223 - [c29]Kaikai Liu, Ting An, Hao Cai, Lirida A. B. Naviner
A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology. EUROCON 2013: 1829-1836 - [c28]Samuel N. Pagliarini
Single event transient mitigation through pulse quenching: Effectiveness at circuit level. ICECS 2013: 121-124 - [c27]Samuel N. Pagliarini
Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis. MWSCAS 2013: 113-116 - [c26]Hao Cai, Hervé Petit, Jean-François Naviner
A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts. NEWCAS 2013: 1-4 - [c25]Samuel N. Pagliarini
Selective hardening against multiple faults employing a net-based reliability analysis. NEWCAS 2013: 1-4 - 2012
- [j15]Hao Cai, Hervé Petit, Jean-François Naviner
A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems. J. Low Power Electron. 8(5): 697-705 (2012) - [j14]Samuel N. Pagliarini
Exploring the feasibility of selective hardening for combinational logic. Microelectron. Reliab. 52(9-10): 1843-1847 (2012) - [c24]Samuel N. Pagliarini
Automatic selective hardening against soft errors: A cost-based and regularity-aware approach. ICECS 2012: 753-756 - [c23]Samuel Nascimento Pagliarini
Selective hardening methodology for combinational logic. LATW 2012: 1-6 - [c22]Kaikai Liu, Tian Ban, Lirida A. B. Naviner
Reliability analysis of a Reed-Solomon decoder. MWSCAS 2012: 438-441 - 2011
- [j13]Pietro Maris Ferreira
A synthesis methodology for AMS/RF circuit reliability: Application to a DCO design. Microelectron. Reliab. 51(4): 765-772 (2011) - [j12]Hao Cai, Hervé Petit, Jean-François Naviner
Reliability aware design of low power continuous-time sigma-delta modulator. Microelectron. Reliab. 51(9-11): 1449-1453 (2011) - [j11]Lirida A. B. Naviner
FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level. Microelectron. Reliab. 51(9-11): 1459-1463 (2011) - [c21]Pietro Maris Ferreira
A new synthesis methodology for reliable RF front-end Design. ISCAS 2011: 2926-2929 - 2010
- [j10]G. G. dos Santos, Elaine Crespo Marques, Lirida A. B. Naviner
Using error tolerance of target application for efficient reliability improvement of digital circuits. Microelectron. Reliab. 50(9-11): 1219-1222 (2010) - [j9]Elaine Crespo Marques, Lirida A. B. Naviner
An efficient tool for reliability improvement based on TMR. Microelectron. Reliab. 50(9-11): 1247-1250 (2010) - [c20]Pietro Maris Ferreira
AMS and RF design for reliability methodology. ISCAS 2010: 3657-3660 - [c19]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
On evaluating the signal reliability of self-checking arithmetic circuits. SBCCI 2010: 109-114
2000 – 2009
- 2008
- [j8]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
Signal probability for reliability evaluation of logic circuits. Microelectron. Reliab. 48(8-9): 1586-1591 (2008) - [j7]Maí Correia R. de Vasconcelos, Denis Teixeira Franco, Lirida A. B. Naviner
Relevant metrics for evaluation of concurrent error detection schemes. Microelectron. Reliab. 48(8-9): 1601-1603 (2008) - [j6]David Camarero, Karim Ben Kalaia, Jean-François Naviner
Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3676-3687 (2008) - [c18]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
Reliability analysis of logic circuits based on signal probability. ICECS 2008: 670-673 - [c17]Maí Correia R. de Vasconcelos, Denis Teixeira Franco, Lirida A. B. Naviner
On the output events in concurrent error detection schemes. ICECS 2008: 978-981 - [c16]Aamir Riaz, Jean-François Naviner
A Novel Approach to Non Coherent UWB Reception. IMTIC 2008: 100-109 - [i1]Lirida Alves de Barros Naviner, Jean-François Naviner, Denis Teixeira Franco, Maí Correia R. de Vasconcelos:
Methods and Metrics for Reliability Assessment. Fault-Tolerant Distributed Algorithms on VLSI Chips 2008 - 2006
- [j5]Denis Teixeira Franco, Jean-François Naviner
Yield and reliability issues in nanoelectronic technologies. Ann. des Télécommunications 61(11-12): 1422-1457 (2006) - [c15]Rayan Mina, Jean-Charles Grasset, Jean-François Naviner
Impact of charge injection on system-level performance of a discrete-time GSM receiver. ICECS 2006: 494-497 - [c14]Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
High-pass Delta Sigma modulator: from system analysis to circuit design. ISCAS 2006 - [c13]Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
A CMOS implementation of time-interleaved high-pass Delta Sigma modulator. ISCAS 2006 - 2005
- [c12]David Camarero, Jean-François Naviner
Calibration of sampling instants in a multiple channel time-interleaved analog-to-digital converter. ICECS 2005: 1-4 - 2004
- [j4]Jean-François Naviner, Amara Amara:
Systems-on-chip for telecommunications. Ann. des Télécommunications 59(7-8): 755-758 (2004) - [c11]David Camarero, Jean-François Naviner
Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters. SBCCI 2004: 228-232 - 2003
- [j3]Sebastian Yuri Cavalcanti Catunda
Designing a programmable analog signal conditioning circuit without loss of measurement range. IEEE Trans. Instrum. Meas. 52(5): 1482-1487 (2003) - [c10]Van-Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
Temporel and spectral analysis of time interleaved high pass sigma delta converter. ICASSP (2) 2003: 453-456 - 2002
- [j2]Patrick Loumeau, Jean-François Naviner, Hervé Petit, Lirida A. B. Naviner, Patricia Desgreys:
Analog to digital conversion: technical aspects. Ann. des Télécommunications 57(5-6): 338-385 (2002) - [c9]Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner:
An interleaved delta-sigma analog to digital converter with digital correction. ICASSP 2002: 4193 - [c8]Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner
A time-interleaved chopper-stabilized delta-sigma analog to digital converter. ICECS 2002: 299-302 - [c7]Van Tam Nguyen, Patrick Loumeau, Jean-François Naviner
Analysis of time-interleaved delta-sigma analog to digital converter. VTC Spring 2002: 1594-1597 - 2001
- [c6]Elizabeth Colin
Antialiasing filtering influences on ADC specifications for radio receivers. ICECS 2001: 1469-1472 - [c5]Elizabeth de Lira Mendes, Patrick Loumeau, Jean-François Naviner
A switched-current sample and hold circuit for low frequency applications. ISCAS (1) 2001: 452-455 - [c4]Elizabeth Colin
Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers. VTC Fall 2001: 2351-2354
1990 – 1999
- 1999
- [c3]T. Vasseaux, B. Huyart, Patrick Loumeau, Jean-François Naviner:
A track&hold-mixer for direct-conversion by subsampling. ISCAS (4) 1999: 584-587 - 1994
- [c2]Jean-Claude Dufourd, Jean-François Naviner:
An Optimizable Model for Process Independent Symbolic Design. EDAC-ETC-EUROASIC 1994: 660 - 1993
- [j1]Jean-François Naviner
Préforme/aGAPE: a synergy between symbolic cell design and assembly. Microprocess. Microprogramming 37(1-5): 11-14 (1993) - 1990
- [c1]Jean-Claude Dufourd, Jean-François Naviner, Francis Jutand:
Preform: A Process Independent Symbolic Layout System. ICCAD 1990: 248-251
Coauthor Index
aka: Lirida Alves de Barros Naviner
aka: Samuel N. Pagliarini
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-05-08 21:03 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: