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Jean-Marc Daveau
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2020 – today
- 2024
- [j8]Esther Goudet
, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche:
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach. J. Electron. Test. 40(3): 291-313 (2024) - [c24]Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Resilience Metric Characterization in Complex Digital Systems. ETS 2024: 1-4 - [c23]Esther Goudet, Luis Peña Treviño, Gutemberg G. dos Santos Júnior, Sayah El Hajji, Fabio Sureau, Lirida Naviner, Jean-Marc Daveau, Philippe Roche:
Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning. SBCCI 2024: 1-5 - 2023
- [c22]Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Temporal Characterization of Register Vulnerability in Digital Circuits. ISVLSI 2023: 1-6 - [c21]Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner
Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. LATS 2023: 1-6 - 2022
- [c20]Tiziano Fiorucci, Giorgio Di Natale, Jean-Marc Daveau, Philippe Roche:
Software Product Reliability Based on Basic Block Metrics Recomposition. IOLTS 2022: 1-5 - 2021
- [c19]Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. DFT 2021: 1-6 - [c18]Tiziano Fiorucci, Jean-Marc Daveau, Giorgio Di Natale, Philippe Roche:
Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems. IOLTS 2021: 1-6
2010 – 2019
- 2018
- [j7]Guenole Lallement
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. IEEE J. Solid State Circuits 53(7): 2088-2100 (2018) - 2017
- [c17]Guenole Lallement, Fady Abouzeid
A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. ESSCIRC 2017: 153-162 - 2016
- [c16]Fady Abouzeid
30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. ESSCIRC 2016: 37-40 - 2015
- [c15]Fady Abouzeid
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. ESSCIRC 2015: 108-111 - [c14]Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid
Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. IRPS 2015: 12 - [c13]Sylvain Clerc, Fady Abouzeid
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370 - [c12]Sylvain Clerc, Mehdi Saligane, Fady Abouzeid
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC 2015: 1-3 - [c11]Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Lirida A. B. Naviner
Partial triplication of a SPARC-V8 microprocessor using fault injection. LASCAS 2015: 1-4 - 2011
- [c10]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner
An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. IOLTS 2011: 98-103 - 2010
- [j6]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner
Fast reliability analysis of combinatorial logic circuits using conditional probabilities. Microelectron. Reliab. 50(9-11): 1215-1218 (2010) - [c9]Oscar Bailan, Umberto Rossi, Anne Wantens, Jean-Marc Daveau, Salvatore Nappi, Philippe Roche:
Verification of soft error detection mechanism through fault injection on hardware emulation platform. DSN Workshops 2010: 113-118 - [c8]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner
Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. ICECS 2010: 263-267
2000 – 2009
- 2008
- [c7]Philippe Roche, Mark Lysinger, Gilles Gasiot, Jean-Marc Daveau, Mehdi Zamanian, Pierre Dautriche:
Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS. IOLTS 2008: 46-48 - 2004
- [c6]Jean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana:
A retargetable register allocation framework for embedded processors. LCTES 2004: 202-210 - 2002
- [c5]Valérie Bertin, Jean-Marc Daveau, Philippe Guillaume, Thierry Lepley, Denis Pilat, Claire Richard, Miguel Santana, Thomas Thery:
FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors. EMSOFT 2002: 382-398 - 2001
- [j5]Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau:
Automating the Design of SOCs Using Cores. IEEE Des. Test Comput. 18(5): 32-45 (2001) - 2000
- [j4]Fabiano Hessel, Pascal Coste, Philippe Le Marrec, Nacer-Eddine Zergainoh, Gabriela Nicolescu, Jean-Marc Daveau, Ahmed Amine Jerraya:
Interlanguage Communication Synthesis for Heterogeneous Specifications. Des. Autom. Embed. Syst. 5(3-4): 223-236 (2000)
1990 – 1999
- 1999
- [c4]Fabiano Hessel
Communication Interface Synthesis for Multilanguage Specifications. IEEE International Workshop on Rapid System Prototyping 1999: 15-20 - 1998
- [j3]Mohamed Abid, Tarek Ben Ismail, Adel Changuel, Carlos A. Valderrama, Mohamed Romdhani, Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya:
Hardware/Software Co-Design Methodology for Design of Embedded Systems. Integr. Comput. Aided Eng. 5(1): 69-84 (1998) - [c3]Jean-Marc Daveau, Gilberto Fernandes Marchioro, Ahmed Amine Jerraya:
Hardware/software co-design of an ATM network interface card: a case study. CODES 1998: 111-115 - 1997
- [j2]Jean-Marc Daveau, Gilberto Fernandes Marchioro, Tarek Ben Ismail, Ahmed Amine Jerraya:
Protocol selection and interface generation for HW-SW codesign. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 136-144 (1997) - [c2]Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya:
Transformational partitioning for co-design of multiprocessor systems. ICCAD 1997: 508-515 - 1996
- [j1]Tarek Ben Ismail, Jean-Marc Daveau, Kevin O'Brien, Ahmed Amine Jerraya:
A system-level communication synthesis approach for hardware/software systems. Microprocess. Microsystems 20(3): 149-157 (1996) - 1995
- [c1]Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya:
Synthesis of system-level communication by an allocation-based approach. ISSS 1995: 150-155
Coauthor Index
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