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ACM Transactions on Design Automation of Electronic Systems, Volume 28
Volume 28, Number 1, January 2023
- José Romero Hung
, Chao Li
DRAGON: Dynamic Recurrent Accelerator for Graph Online Convolution. 1:1-1:27 - Svetlana Minakova, Todor P. Stefanov:
Memory-Throughput Trade-off for CNN-Based Applications at the Edge. 2:1-2:26 - Vidya A. Chhabria
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. 3:1-3:27 - Jan Spieck, Stefan Wildermann, Jürgen Teich:
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. 4:1-4:40 - Chunqiao Li
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid. 5:1-5:31 - Chenglong Huang
Rescuing ReRAM-based Neural Computing Systems from Device Variation. 6:1-6:17 - Bo Ding
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. 7:1-7:21 - Junwei Zeng
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device. 8:1-8:16 - Sourav Das
CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications. 9:1-9:32 - Zhuoran Song
E2-VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition. 10:1-10:21 - Zhiqiang Zhao
A Multilevel Spectral Framework for Scalable Vectorless Power/Thermal Integrity Verification. 11:1-11:25 - Kai Huang
Structured Dynamic Precision for Deep Neural Networks Quantization. 12:1-12:24 - Farhad Ebrahimi-Azandaryani
Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode. 13:1-13:14
Volume 28, Number 2, March 2023
- Yibo Lin
Introduction to the Special Issue on Machine Learning for CAD/EDA. 14:1-14:2 - Daniela Sánchez
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications. 15:1-15:27 - David Selasi Koblah, Rabin Yu Acharya
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation. 16:1-16:57 - Shaoze Fan
Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search. 17:1-17:33 - Ling-Yen Song
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. 18:1-18:22 - Yaguang Li
Performance-driven Wire Sizing for Analog Integrated Circuits. 19:1-19:23 - Jiawen Cheng
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis. 20:1-20:16 - Yiting Liu
GraphPlanner: Floorplanning with Graph Neural Network. 21:1-21:24 - Chenlei Fang
Efficient Test Chip Design via Smart Computation. 22:1-22:31 - Erika Susana Alcorta Lozano
Learning-based Phase-aware Multi-core CPU Workload Forecasting. 23:1-23:27 - Benzheng Li
Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs. 24:1-24:16 - Lorenzo Ferretti
Graph Neural Networks for High-Level Synthesis Design Space Exploration. 25:1-25:20 - Felix Last
Training PPA Models for Embedded Memories on a Low-data Diet. 26:1-26:24 - Wei W. Xing
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation. 27:1-27:26 - Ruochen Dai
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don't Care Transitions. 28:1-28:31 - Zhisheng Chen
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage. 29:1-29:30
Volume 28, Number 3, May 2023
- Dwaipayan Choudhury
Accelerating Graph Computations on 3D NoC-Enabled PIM Architectures. 30:1-30:16 - Jayoung Lee
Virtuoso: Energy- and Latency-aware Streamlining of Streaming Videos on Systems-on-Chips. 31:1-31:32 - Ashish Reddy Bommana
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. 32:1-32:35 - Chun-Chieh Yang
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension. 33:1-33:21 - Shanshi Huang
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators. 34:1-34:23 - Lang Feng
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design. 35:1-35:20 - Junpeng Wang
DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems. 36:1-36:30 - Bhawna Rawat
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications. 37:1-37:14 - Danny Pereira
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach. 38:1-38:33 - Yanze Huang
Component Fault Diagnosability of Hierarchical Cubic Networks. 39:1-39:19 - Qi Nie
CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks. 40:1-40:36 - Ricardo Gonzalez de Oliveira
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles. 41:1-41:37 - Mervat M. A. Mahmoud
Low-energy Pipelined Hardware Design for Approximate Medium Filter. 42:1-42:21 - Jordi Cardona
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems. 43:1-43:34 - Yajuan Du
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics. 44:1-44:25 - Yuhao Zhou
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm. 45:1-45:16 - Senling Wang
Test Point Insertion for Multi-Cycle Power-On Self-Test. 46:1-46:21 - Trung Le
Polling-Based Memory Interface. 47:1-47:23
Volume 28, Number 4, July 2023
- Igor L. Markov
Guest Editor's Introduction: Machine Learning for VLSI Physical Design. 48:1-48:3 - Suhas Krishna Kashyap
IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages. 49:1-49:23 - Daijoon Hyun
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking. 50:1-50:19 - Dmitry Utyamishev
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks. 51:1-51:19 - Chung-Kuan Cheng
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs. 52:1-52:31 - Ping-Wei Huang
Routability-driven Power/Ground Network Optimization Based on Machine Learning. 53:1-53:27 - Xiao Dong
Worst-case Power Integrity Prediction Using Convolutional Neural Network. 54:1-54:19 - Yi-Chen Lu
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation. 55:1-55:22 - Dingcheng Yang
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction. 56:1-56:22 - Tianshu Hou
A Deep Learning Framework for Solving Stress-based Partial Differential Equations in Electromigration Analysis. 57:1-57:20 - Qing Zhang
CmpCNN: CMP Modeling with Transfer Learning CNN Architecture. 58:1-58:18 - Ahmad O. Aseeri
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions. 59:1-59:18
- Abhiroop Bhattacharjee
SwitchX: Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars. 60:1-60:21 - Po-Hsuan Huang
SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference. 61:1-61:28 - Abrar A. Ibrahim
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation. 62:1-62:26 - Bruno Ferres
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. 63:1-63:31 - Muhammad Imran Khan
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems. 64:1-64:17 - Xu He
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits. 65:1-65:22 - Reza Kazerooni-Zand
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference. 66:1-66:25 - Cheng Chu, Cheng Liu, Dawen Xu, Ying Wang, Tao Luo, Huawei Li, Xiaowei Li:
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. 67:1-67:23
Volume 28, Number 5, September 2023
- Iris Hui-Ru Jiang
Introduction to the Special Section on Advances in Physical Design Automation. 68:1-68:3 - Ramprasath Srinivasa Gopalakrishnan
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. 69:1-69:25 - Min Wei
Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs. 70:1-70:24 - Stefan Hougardy
A Fast Optimal Double-row Legalization Algorithm. 71:1-71:26 - Siad Daboul
Global Interconnect Optimization. 72:1-72:24 - Zhonghua Zhou
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing. 73:1-73:25 - Su Zheng
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization. 74:1-74:23 - Gauthaman Murali
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers. 75:1-75:22 - Pruek Vanna-Iampikul
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs. 76:1-76:26 - Jun-Sheng Wu
ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design. 77:1-77:26 - Yanjiang Liu
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack. 78:1-78:17
- Erfan Aghaeekiasaraee
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes. 79:1-79:42 - Binwu Zhu
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction. 80:1-80:18 - Angeliki Kritikakou
Mitigating Mode-switch through Run-time Computation of Response Time. 81:1-81:26 - Zilu Wang
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays. 82:1-82:32 - Mohammad Mezanur Rahman Monjur, Joshua Calzadillas
Hardware Security Risks and Threat Analyses in Advanced Manufacturing Industry. 83:1-83:22 - Gaurav Narang
Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework. 84:1-84:21 - Jingweijia Tan
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations. 85:1-85:21 - Meng-Jing Li
A Constructive Approach for Threshold Function Identification. 86:1-86:19 - Nuzhat Yamin
Uncertainty-aware Energy Harvest Prediction and Management for IoT Devices. 87:1-87:33
Volume 28, Number 6, November 2023
- Ruisi Zhang
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings. 88:1-88:32
- Huaixi Lu
SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications. 89:1-89:24 - Xu He
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization. 90:1-90:23 - Yajing Chang
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack. 91:1-91:19 - Stylianos I. Venieris
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation. 92:1-92:31 - Muhtadi Choudhury
Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming. 93:1-93:26 - Ayush Dahiya
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM. 94:1-94:15 - Mahum Naseer
QuanDA: GPU Accelerated Quantitative Deep Neural Network Analysis. 95:1-95:21 - Bhawna Rawat
A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application. 96:1-96:14 - S. Sivakumar
Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC. 97:1-97:24 - Khalil Esper
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. 98:1-98:20 - Debabrata Senapati
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. 99:1-99:22 - Qinghui Hong
Programmable In-memory Computing Circuit of Fast Hartley Transform. 100:1-100:23 - Debraj Kundu
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization. 101:1-101:26 - Shanglin Zhou
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning. 102:1-102:19 - Bo Ding
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. 103:1-103:26 - Wenxiong Lin
Sequential Routing-based Time-division Multiplexing Optimization for Multi-FPGA Systems. 104:1-104:10 - Pushkar Praveen
Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology. 105:1-105:29
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