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Arvind K. Sharma
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2020 – today
- 2024
- [c30]Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath
, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar:
Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC 2024: 665-670 - 2023
- [j12]Mohammad Haider Syed, Kamal Upreti
Addressing image and Poisson noise deconvolution problem using deep learning approaches. Comput. Intell. 39(4): 577-591 (2023) - [j11]Lomash Chandra Acharya
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2657-2663 (2023) - [j10]Nibedita Karmokar
Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2782-2795 (2023) - [j9]Kishor Kunal
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2801-2814 (2023) - [j8]Yaguang Li
Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. 28(2): 19:1-19:23 (2023) - [j7]Ramprasath Srinivasa Gopalakrishnan
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28(5): 69:1-69:25 (2023) - [c29]Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu:
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. APCCAS 2023: 105-109 - [c28]Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun:
AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. DATE 2023: 1-6 - [c27]Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC 2023: 69-72 - [c26]Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu:
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. SMACD 2023: 1-4 - 2022
- [c25]Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC 2022: 114-121 - [c24]Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary
Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. DATE 2022: 166-171 - [c23]Ramprasath S
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD 2022: 159-166 - 2021
- [j6]Tonmoy Dhar, Kishor Kunal
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38(2): 8-18 (2021) - [j5]Pravin Kshirsagar, Hariprasath Manoharan, Vineet Tirth
Automation Monitoring With Sensors For Detecting Covid Using Backpropagation Algorithm. KSII Trans. Internet Inf. Syst. 15(7): 2414-2433 (2021) - [c22]Tonmoy Dhar, Jitesh Poojary
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC 2021: 158-163 - [c21]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar:
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE 2021: 1224-1229 - [c20]Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani:
Analog Layout Generation using Optimized Primitives. DATE 2021: 1234-1239 - [c19]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - [c18]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar:
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD 2021: 1-9 - [c17]Tonmoy Dhar, Kishor Kunal
Machine Learning Techniques in Analog Layout Automation. ISPD 2021: 71-72 - [c16]Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu:
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. ISQED 2021: 251-256 - [c15]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD 2021: 1-6 - 2020
- [c14]Kishor Kunal
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE 2020: 55-60 - [c13]Tonmoy Dhar, Kishor Kunal
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD 2020: 54:1-54:2 - [c12]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD 2020: 135:1-135:9 - [c11]Kishor Kunal
Learning from Experience: Applying ML to Analog Circuit Design. ISPD 2020: 55 - [c10]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI 2020: 24-29 - [i1]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz:
ALIGN: A System for Automating Analog Layout. CoRR abs/2008.10682 (2020)
2010 – 2019
- 2019
- [j4]Chaudhry Indra Kumar
An energy-efficient variation aware self-correcting latch. Microelectron. J. 84: 67-78 (2019) - [j3]Chaudhry Indra Kumar
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2170-2179 (2019) - [c9]Kishor Kunal
ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC 2019: 77 - 2018
- [c8]Arvind Kumar Sharma, Naushad Alam
UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective. PRIME 2018: 57-60 - 2016
- [j2]Baljit Kaur
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectron. J. 53: 45-55 (2016) - [c7]Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu:
A novel energy-efficient self-correcting methodology employing INWE. SMACD 2016: 1-4 - [c6]Sayyaparaju Sagar Varma, Arvind Kumar Sharma, Bulusu Anand:
An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis. SMACD 2016: 1-4 - 2015
- [c5]Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand:
Efficient static D-latch standard cell characterization using a novel setup time model. ISQED 2015: 371-378 - [c4]Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur
Timing model for two stage buffer and its application in ECSM characterization. VDAT 2015: 1-6 - [c3]Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. VDAT 2015: 1-6 - 2014
- [c2]Bijay Kumar Dalai, N. Karnnan, Arvind Kumar Sharma, Bulusu Anand:
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect. VDAT 2014: 1-2
2000 – 2009
- 2009
- [c1]Amol Vasudeva
Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator. CICSyN 2009: 220-225 - 2006
- [j1]Michael V. Aust, Arvind K. Sharma, Owen Fordham, Ronald Grundbacher, Richard To, Roger S. Tsai, Richard Lai:
A 2.8-W Q-Band High-Efficiency Power Amplifier. IEEE J. Solid State Circuits 41(10): 2241-2247 (2006)
Coauthor Index
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