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Zhichun Zhu
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2020 – today
- 2023
- [j13]Peiyun Wu
, Trung Le
Redundant Array of Independent Memory Devices. IEEE Comput. Archit. Lett. 22(2): 181-184 (2023) - [j12]Trung Le
Polling-Based Memory Interface. ACM Trans. Design Autom. Electr. Syst. 28(3): 47:1-47:23 (2023) - 2022
- [c21]Muhammad M. Rafique, Zhichun Zhu:
Dynamic Page Policy Using Perceptron Learning. MEMSYS 2022: 2:1-2:11 - 2021
- [j11]Muhammad M. Rafique
Memory-Side Prefetching Scheme Incorporating Dynamic Page Mode in 3D-Stacked DRAM. IEEE Trans. Parallel Distributed Syst. 32(11): 2734-2747 (2021) - [c20]Trung Le, Zhao Zhang, Zhichun Zhu:
POMI: Polling-Based Memory Interface for Hybrid Memory System. ICCD 2021: 447-455 - 2020
- [c19]Majed Valad Beigi, Bahareh Pourshirazi, Gokhan Memik, Zhichun Zhu:
DeepSwapper: A Deep Learning Based Page Swap Management Scheme for Hybrid Memory Systems. PACT 2020: 353-354
2010 – 2019
- 2019
- [j10]Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik:
Writeback-Aware LLC Management for PCM-Based Main Memory Systems. ACM Trans. Design Autom. Electr. Syst. 24(2): 18:1-18:19 (2019) - [c18]Muhammad M. Rafique, Zhichun Zhu:
FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAM. MEMSYS 2019: 373-382 - 2018
- [c17]Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik:
WALL: A writeback-aware LLC management for PCM-based main memory systems. DATE 2018: 449-454 - [c16]Muhammad M. Rafique, Zhichun Zhu:
CAMPS: Conflict-Aware Memory-Side Prefetching Scheme for Hybrid Memory Cube. ICPP 2018: 63:1-63:9 - 2017
- [c15]Bahareh Pourshirazi, Zhichun Zhu:
NEMO: an energy-efficient hybrid main memory system for mobile devices. MEMSYS 2017: 351-362 - 2016
- [c14]Bahareh Pourshirazi, Zhichun Zhu:
Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System. IPDPS 2016: 566-575 - 2014
- [j9]Kun Fang, Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu:
Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture. IEEE Trans. Computers 63(6): 1500-1512 (2014) - [c13]Suyu Zhang, Zhichun Zhu:
Access-Aware Memory Thermal Management. NAS 2014: 268-274 - 2013
- [j8]Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang:
Thermal Modeling and Management of DRAM Systems. IEEE Trans. Computers 62(10): 2069-2082 (2013) - [c12]Kun Fang, Zhichun Zhu:
Conservative row activation to improve memory power efficiency. ICS 2013: 81-90 - 2011
- [c11]Kun Fang, Long Chen, Zhao Zhang, Zhichun Zhu:
Memory Architecture for Integrating Emerging Memory Technologies. PACT 2011: 403-412 - 2010
- [j7]Hongzhong Zheng, Zhichun Zhu:
Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors. IEEE Trans. Computers 59(8): 1033-1046 (2010) - [c10]Kun Fang, Hongzhong Zheng, Zhichun Zhu:
Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture. ICPP 2010: 21-29
2000 – 2009
- 2009
- [c9]Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu:
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. ISCA 2009: 255-266 - 2008
- [c8]Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu:
Memory Access Scheduling Schemes for Systems with Multi-Core Processors. ICPP 2008: 406-413 - [c7]Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu:
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. MICRO 2008: 210-221 - [c6]Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang:
Software thermal management of dram memory for multicore systems. SIGMETRICS 2008: 337-348 - 2007
- [c5]Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang:
Thermal modeling and management of DRAM memory systems. ISCA 2007: 312-322 - [c4]Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang, Howard David:
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. ISPASS 2007: 94-104 - 2005
- [j6]Zhichun Zhu, Xiaodong Zhang:
Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption. IEEE Micro 25(4): 10-19 (2005) - [c3]Zhichun Zhu, Zhao Zhang:
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. HPCA 2005: 213-224 - 2004
- [j5]Zhao Zhang, Zhichun Zhu, Xiaodong Zhang:
Design and Optimization of Large Size and Low Overhead Off-Chip Caches. IEEE Trans. Computers 53(7): 843-855 (2004) - 2002
- [j4]Zhichun Zhu, Xiaodong Zhang:
Access-Mode Predictions for Low-Power Cache Design. IEEE Micro 22(2): 58-71 (2002) - [c2]Zhichun Zhu, Zhao Zhang, Xiaodong Zhang:
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. HPCA 2002: 107-116 - 2001
- [j3]Zhao Zhang, Zhichun Zhu, Xiaodong Zhang:
Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts. J. Instr. Level Parallelism 3 (2001) - [j2]Zhao Zhang, Zhichun Zhu, Xiaodong Zhang:
Cached DRAM for ILP Processor Memory Access Latency Reduction. IEEE Micro 21(4): 22-32 (2001) - 2000
- [j1]Xing Du, Xiaodong Zhang, Zhichun Zhu:
Memory Hierarchy Considerations for Cost-Effective Cluster Computing. IEEE Trans. Computers 49(9): 915-933 (2000) - [c1]Zhao Zhang, Zhichun Zhu, Xiaodong Zhang:
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. MICRO 2000: 32-41
Coauthor Index
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