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VLSI-DAT 2012: Hsinchu, Taiwan
- Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, April 23-25, 2012. IEEE 2012, ISBN 978-1-4577-2080-2
- Michel Brillouët, Shyh-Jye Jou, C. Patrick Yue:
Welcome from the general chairs. 1 - An-Yeu Wu
, Li-C. Wang
Foreword. 1-2 - Ya-Qin Zhang:
Advances in computing. 1 - Philippe Magarshack, Andreia Cathelin:
Gaining 10x in energy efficiency in the next decade in consumer products. 1-2 - Gary Huang:
Powerful smartphone solutions unleashing new technology innovations. 1 - Peter Lemmens:
Disruptive technologies for the future generation smart systems. 1 - Tim Whitfield:
The 2012 ARM powered compute subsystem - delivering the smart handheld platform. 1 - Doug Kwan, Jing Yu, Bhaskar Janakiraman:
Google's C/C++ toolchain for smart handheld devices. 1-4 - Lin Lin, Weber Chien:
Emerging touch techniques in smart handheld device. 1-2 - Hidemi Takasu:
Silicon Carbide devices open a new era of power electronics. 1-2 - Leo Lorenz:
Power semiconductor-driving technology for high power green electronic systems. 1-2 - Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang:
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. 1-4 - Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang:
A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. 1-4 - Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih:
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. 1-4 - Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang:
A slew rate self-adjusting 2×VDD output buffer With PVT compensation. 1-4 - Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto:
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS. 1-4 - Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda:
A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. 1-4 - Chia-Chi Ho, Tai-Cheng Lee:
A 10-bit 200-MS/s reconfigurable pipelined A/D converter. 1-4 - Jen-Huan Tsai, Yen-Ju Chen, Yan-Fong Lai, Meng-Hung Shen, Po-Chiun Huang:
A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques. 1-4 - Takayasu Sakurai:
Ambient electronics and ultra-low power LSI design. 1-31 - Sheng-Wei Fan, Jia-Wai Chen, Jiun-In Guo:
Low bandwidth HD1080@60FPS JPEG-XR transform design. 1-4 - Liang-Chi Chiu, Tian-Sheuan Chang
A lossless embedded compression codec engine for HD video decoding. 1-4 - Fu-Chen Chen, Yung-Lin Huang
Hardware-efficient true motion estimator based on Markov Random Field motion vector correction. 1-4 - Nasirul Chowdhury, Jeff Wight, Christopher Mozak, Nasser A. Kurd:
Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm. 1-4 - Kuo-Wei Cheng, Chin Yin, Chih-Cheng Hsieh, Wen-Hsu Chang, Hann-Huei Tsai, Chin-Fong Chiu:
Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor. 1-4 - I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A fast-locking phase-locked loop using CP control and gated VCO. 1-4 - Yi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang:
A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. 1-4 - Yung-Kuei Lu, Ming-Der Shieh:
Efficient architecture for Reed-Solomon decoder. 1-4 - Xi-Rui Wang, Hsi-Pin Ma, Jen-Yuan Hsu, Pangan Ting:
Large set construction of user uplink ranging codes for M2M applications. 1-4 - Tzon-Tzer Lu, Hua-Chin Lee, Chao-Shiun Wang, Chorng-Kuang Wang:
A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascode. 1-4 - Chih-Ting Yeh, Ming-Dou Ker:
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. 1-4 - Shin-Jye Hsu, Che-Yu Lu, Chung-Chih Hung:
40MHz Gm-C filter with high linearity OTA for wireless applications. 1-4 - Ping K. Ko, C. Patrick Yue
The evolution of fabless IC industry in China: Past, present, and future. 1 - Kevin J. Nowka
Transforming memory systems: Optimizing for client value on emerging workloads. 1-2 - Roberto Bez, Paolo Cappelletti:
Emerging memory technology perspective. 1-2 - Brian Lee:
Review of 3D high density storage class memory (SCM) architecture. 1 - Gabriel H. Loh:
Computer architecture for die stacking. 1-2 - Cong Hao, Song Chen
Port assignment for interconnect reduction in high-level synthesis. 1-4 - Zheng Wang, Xiao Wang, Anupam Chattopadhyay, Zoltan Endre Rakosi:
ASIC synthesis using Architecture Description Language. 1-4 - Yuan-Chuan Steven Chen, Dave Budka, Auston Gibertini, Dan Bockelman, Yutien Lin:
Design validation on multiple-core CPU supported low power states using platform based infrared emission microscopy (PIREM) technique. 1-4 - Xin-Tian Wu, Kai-Hua Hsu, Lynn C.-L. Chang, Charles H.-P. Wen:
Spatial-correlation-aware soft error rate analysis using quasi-importance sampling. 1-4 - Jyun-Cheng Wu, Lei Chen, Tzi-Dar Chiueh:
Design of a real-time software-based GPS baseband receiver using GPU acceleration. 1-4 - Yun-Yen ChenWu, Hsi-Pin Ma, Chaitali Biswas, Dejan Markovic:
Universal architecture prototype for patient-centric medical environment. 1-4 - Yi-Jun Liu, Chih-Chyau Yang, Shih-Lun Chen, Chun-Chieh Chiu, Chien-Ming Wu, Chun-Ming Huang:
An efficient memory controller for 3D heterogeneous integration platform. 1-4 - Ching-Hao Lin, Kuo-Chiang Chang, Ming-Hsun Chuang, Chih-Wei Liu:
Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids. 1-4 - Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu
3D-IC BISR for stacked memories using cross-die spares. 1-4 - Wei-Cheng Lien
Routing-efficient implementation of an internal-response-based BIST architecture. 1-4 - Xuefeng Zhu, Huawei Li, Xiaowei Li:
Statistical SDFC: A metric for evaluating test quality of small delay faults. 1-4 - B.-Y. Jan, J.-L. Huang:
A fault-tolerant PE array based matrix multiplier design. 1-4 - Shing-Yu Chen, Chi-Neng Wen, Geng-Hau Yang, Wen-Ben Jone, Tien-Fu Chen:
IMITATOR: A deterministic multicore replay system with refining techniques. 1-4 - Kun-Chih Chen
Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems. 1-4 - Shui-An Wen, Chun-Chin Chen, Shing-Wu Tung:
A power management technology for mobile embedded system. 1-4 - Guan-Ru Li, Bo-Cheng Charles Lai:
A highly parallel design of image surface layout recovering on GPGPU. 1-4 - Mu-Shun Matt Lee, Yi-Chu Liu, Wan-Rong Wu, Chien-Nan Jimmy Liu:
Peak wake-up current estimation at gate-level with standard library information. 1-4 - Sheng-Jhih Jiang, Chan-Liang Wu, Tsung-Yi Ho
A nonlinear optimization methodology for resistor matching in analog integrated circuits. 1-4 - Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou:
3-D centric technology and realization with TSV. 1-4 - Ching-Che Chung
A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology. 1-4 - Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng:
Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. 1-4 - Shih-Nung Wei, Yi-Ming Wang, Jyun-Hua Peng, Yuandi Surya:
A range extending delay-recycled clock skew-compensation and/or duty-cycle-correction circuit. 1-4 - Ching-Hwa Cheng, Jiun-In Guo:
A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism. 1-4 - Chi-Cheng Ju, Yung-Chang Chang, Chih-Ming Wang, Chun-Chia Chen, Hue-Min Lin, Chia-Yun Cheng, Fred Chiu, Sheng-Jen Wang, Tsu-Ming Liu, Chung-Hung Tsai:
A 363-µW/fps power-aware green multimedia processor for mobile applications. 1-4 - Kevin Ho, Tsung-Yi Chou, Po-Kai Chen, David J. Liou:
High speed DDR2/3 PHY and dual CPU core design for 28nm SoC. 1-5 - Simon Jiang, Frankwell Lin:
The best SoC solution with AndesCore and Andes's platform. 1-4 - Chih-Wea Wang, Chen-Tung Lin, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu:
Test for more than pass/fail using on-chip temperature sensor. 1-4 - Chien-Lin Huang, Nian-Shyang Chang, Chi-Shi Chen, Chun-Pin Lin, Chien-Ming Wu, Chun-Ming Huang:
A novel design methodology for hybrid process 3D-IC. 1-4 - Tung-Chieh Chen, Ta-Yu Kuan, Chung-Che Hsieh, Chi-Chen Peng:
Challenges and solutions in modern analog placement. 1-4 - K. Lawrence Loh:
Technology and design challenges for smartphone SOCs. 1 - Magdy S. Abadir, Nik Sumikawa, Wen Chen, Li-C. Wang:
Data mining based prediction paradigm and its applications in design automation. 1 - David Z. Pan, Jhih-Rong Gao, Bei Yu:
VLSI CAD for emerging nanolithography. 1-4 - Li-Jung Chang, Yu-Jen Huang, Jin-Fu Li:
Area and reliability efficient ECC scheme for 3D RAMs. 1-4 - Po-Hsiang Lan, Yao-Jun Kuo, Po-Chiun Huang:
An area-efficient CMOS switching converter with on-chip LC filter using feedforward ripple cancellation technique. 1-4 - Cihun-Siyong Alex Gong, Kai-Wen Yao, Jyun-Yue Hong, Muh-Tian Shiue:
On investigation into A CMOS-process-based high-voltage driver applied to implantable microsystem. 1-4 - Rongxiang Wu, Salahuddin Raju, Mansun Chan
Wireless power link design using silicon-embedded inductors for brain-machine interface. 1-4 - Ruili Wu, Yan Li, Jerry Lopez, Donald Y. C. Lie:
A monolithic 1.85GHz 2-stage sige power amplifier with envelope tracking for improved linear power and efficiency. 1-4 - Kuei-Cheng Lin, Hwann-Kaeo Chiou, Po-Chang Wu, Chu-Jung Sha, Chun-Lin Ko, Da-Chiang Chang, Ying-Zong Juang:
Variable gain active predistorter with linearity enhancement for a 2.4 GHz SiGe HBT power amplifier design. 1-4 - Wei-Ning Liu, Tsung-Hsien Lin
An energy-efficient ultra-wideband transmitter with an FIR pulse-shaping filter. 1-4 - Chun-Lin Ko, Chieh-Pin Chang, Chien-Nan Kuo, Da-Chiang Chang, Ying-Zong Juang:
A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines. 1-4 - Yin-Tsung Hwang, Sung-Jun Tsai, Yi-Yo Chen:
Design and implementation of an optical OFDM baseband receiver in FPGA. 1-4 - Cheng-Ta Wu, Feng-Xiang Huang, Kuan-Fu Kuo, Ing-Jer Huang:
An OCP-AHB bus wrapper with built-in ICE support for SOC integration. 1-4 - WeiXiang Tang, Yursun Hsu:
Design of a pipelined clos network with late release scheme. 1-4 - Chien-Hui Liao, Hung-Pin Wen:
Performance validation of dynamic-remapping-based task scheduling on 3D multi-core processors. 1-4 - Hui Geng, Yiyu Shi, Ming Dong, Runsheng Liu:
A master-slave SoC structure for HMM based speech recognition. 1-4 - Yu-Jen Huang, Jin-Fu Li, Che-Wei Chou:
Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. 1-4 - Chih-Yao Hsu, Chun-Yi Kuo, James Chien-Mo Li, Krishnendu Chakrabarty
3D IC test scheduling using simulated annealing. 1-4 - Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, Chin-Fu Lin:
A 1-V, 44.6 ppm/°C bandgap reference with CDS technique. 1-4 - Jia-Nan Tai, Hsin-Shu Chen
A highly integrated class-D amplifier using driver delay hysteresis control. 1-4 - Tao Jiang, Kangmin Hu, Patrick Yin Chiang:
A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing. 1-4 - Chih-Kai Yang, Chi-Hsuan Hsieh, Yuan-Hao Huang:
An energy-saving spectrum sensing processor based on partial discrete wavelet packet transform. 1-4 - Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto:
DVB-T2 LDPC decoder with perfect conflict resolution. 1-4 - Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A low cost DPA-resistant 8-bit AES core based on ring oscillators. 1-4 - Guixuan Liang, Danping He, Jorge Portilla
A hardware in the loop design methodology for FPGA system and its application to complex functions. 1-4
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