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Chun-Pin Lin
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2020 – today
- 2024
- [j3]Yu-Hsuan Tsai, Yi-Cheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Shi-Hao Chen, Chi-Shi Chen, Chia-Hsiang Yang:
A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices. IEEE J. Solid State Circuits 59(11): 3816-3826 (2024) - [j2]Wen-Cong Huang, I-Ting Lin, Ying-Sheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality. IEEE J. Solid State Circuits 59(11): 3840-3852 (2024) - 2023
- [c13]Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu
, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. ISSCC 2023: 44-45 - [c12]I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots. ISSCC 2023: 46-47 - [c11]Cheng-Yan Du, Chieh-Fu Tsai, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. ISSCC 2023: 332-333 - 2022
- [c10]Wen-Cong Huang, I-Ting Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality. VLSI Technology and Circuits 2022: 42-43 - 2021
- [j1]Yi-Chung Wu
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. IEEE J. Solid State Circuits 56(1): 123-135 (2021) - [c9]Yu-Tung Liu, ChuKing Kung
A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS. ESSCIRC 2021: 107-110 - [c8]Yu-Tung Liu, ChuKing Kung, Ming-Hang Hsieh, Hsiu-Wen Wang, Chun-Pin Lin, Chao-Yang Yu, Chi-Shi Chen, Tzi-Dar Chiueh:
A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS. ESSDERC 2021: 107-110 - 2020
- [c7]Yi-Chung Wu
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. ISSCC 2020: 322-324
2010 – 2019
- 2018
- [c6]Shun-Wen Cheng, Chun-Pin Lin, Chi-Shi Chen, Wei-Chang Tsai:
Universal CMOS Diamond-Graph Circuit for Embedded Computing. SoCC 2018: 206-212 - 2017
- [c5]Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS 2017: 1-4 - 2013
- [c4]Chun-Chieh Chiu, Chih-Hsing Lin, Chih-Chyau Yang, Yi-Jun Liu, Ssu-Ying Chen, Jin-Ju Chue, Chih-Ting Kuo, Gang-Neng Sung, Chun-Pin Lin, Chien-Ming Wu, Chun-Ming Huang:
Morpack Cube: A portable 3D heterogeneous system integration platform. SoCC 2013: 197-202 - 2012
- [c3]Chih-Ting Kuo, Chun-Yu Chen, Yu-Tsang Chang, Chun-Pin Lin, Chien-Ming Wu, Chun-Ming Huang:
CIC signal processing embedded system a modulizable platform for multi-domain signal processing. EMBC 2012: 2849-2852 - [c2]Chien-Lin Huang, Nian-Shyang Chang, Chi-Shi Chen, Chun-Pin Lin, Chien-Ming Wu, Chun-Ming Huang:
A novel design methodology for hybrid process 3D-IC. VLSI-DAT 2012: 1-4
2000 – 2009
- 2000
- [c1]Kuo-Hsing Cheng, Chih-Sheng Huang, Chun-Pin Lin:
The design and implementation of DCT/IDCT chip with novel architecture. ISCAS 2000: 741-744
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