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2020 – today
- 2024
- [c79]Yao-Hui Su, Ming-Der Shieh, Chia-Chi Tsai:
Target-Aware Siamese Networks Based on Masked Attention Mechanism for Visual Object Tracking. MIPR 2024: 28-34 - [i1]Jiun-Man Chen, Yu-Hsuan Chao, Yu-Jie Wang, Ming-Der Shieh, Chih-Chung Hsu, Wei-Fen Lin:
QuantTune: Optimizing Model Quantization with Adaptive Outlier-Driven Fine Tuning. CoRR abs/2403.06497 (2024) - 2023
- [j40]Shen-Ming Chung
, Ming-Der Shieh, Tzi-Cker Chiueh:
FETCH: A cloud-native searchable encryption scheme enabling efficient pattern search on encrypted data within cloud services. Int. J. Commun. Syst. 36(1) (2023) - [c78]Kuan-Yu Chen, Ming-Der Shieh:
VLSI Design of Number Theoretic Transform for BGV Fully Homomorphic Encryption. ICCE-Taiwan 2023: 537-538 - [c77]Kuan-Yu Chen, Ming-Der Shieh:
Area-Efficient VLSI Architecture of Key Switching for BGV Fully Homomorphic Encryption. ICECS 2023: 1-4 - 2022
- [j39]Cheng-Wen Wu
Enhancing Fan Engagement in a 5G Stadium With AI-Based Technologies and Live Streaming. IEEE Syst. J. 16(4): 6590-6601 (2022) - [j38]Yu-Hsiang Lin
Locating Image Objects With Probability Distributions. IEEE Signal Process. Lett. 29: 2722-2726 (2022) - [c76]Kuan-Hsun Duh, Cheng-Wen Wu
Aging Impact of Power MOSFETs in Charger with Different Operation Frequency. ATS 2022: 54-59 - [c75]Yu-You Chou, Cheng-Wen Wu
Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration. ATS 2022: 66-71 - [c74]Shi-Yong Wu, Kuan-Yu Chen, Ming-Der Shieh:
Efficient VLSI Architecture of Bluestein's FFT for Fully Homomorphic Encryption. ISCAS 2022: 2242-2245 - [c73]Ya-Chi Cheng, Pai-Yu Tan
Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method. ITC 2022: 601-608 - [c72]Ya-Chi Cheng, Pai-Yu Tan
A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips. ITC-Asia 2022: 19-24 - [c71]Shian-Yu Lin, Pai-Yu Tan
Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability. ITC-Asia 2022: 25-30 - 2021
- [j37]Chun-Wei Chen
Edge-Based Meta-ICP Algorithm for Reliable Camera Pose Estimation. IEEE Access 9: 89020-89028 (2021) - [c70]Yi-Fu Tseng, Ming-Der Shieh, Chih-Hung Kuo:
Low Latency Design of Polar Decoder for Flash Memory. ICCE-TW 2021: 1-2 - [c69]Chien-Chih Huang, Jyun-Neng Ji, Ming-Der Shieh:
On Compare-and-Swap Optimization for Fully Homomorphic Encrypted Data. ISCAS 2021: 1-4 - 2020
- [j36]Shen-Ming Chung
uFETCH: A Unified Searchable Encryption Scheme and Its Saas-Native to Make DBMS Privacy-Preserving. IEEE Access 8: 93894-93906 (2020) - [c68]Hsuan-Jui Hsu, Ming-Der Shieh:
VLSI Architecture of Polynomial Multiplication for BGV Fully Homomorphic Encryption. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c67]Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen:
Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. DDECS 2019: 1-4 - [c66]Jyun-Neng Ji, Ming-Der Shieh:
Efficient Comparison and Swap on Fully Homomorphic Encrypted Data. ISCAS 2019: 1-4 - 2018
- [j35]Jheng-Hao Ye, Ming-Der Shieh
Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1727-1736 (2018) - [c65]Chun-Wei Chen, Wen-Yuan Hsiao, Ting-Yu Lin, Jonas Wang, Ming-Der Shieh:
Fast Keyframe Selection and Switching for ICP-based Camera Pose Estimation. ISCAS 2018: 1-4 - [c64]Jheng-Hao Ye, Si-Quan Chen, Ming-Der Shieh:
Minimizing ESOP Expressions for Fully Homomorphic Encryption. ISCAS 2018: 1-4 - [c63]Shen-Ming Chung, Ming-Der Shieh, Tzi-Cker Chiueh:
A Security Proxy to Cloud Storage Backends Based on an Efficient Wildcard Searchable Encryption. SC² 2018: 127-130 - [c62]Jheng-Hao Ye, Ming-Der Shieh:
High-performance NTT architecture for large integer multiplication. VLSI-DAT 2018: 1-4 - 2017
- [c61]Chun-Wei Chen, Ming-Der Shieh, Juin-Ming Lu, Hsun-Lun Huang, Yao-Hua Chen:
Content-aware line-based power modeling methodology for image signal processor. SoCC 2017: 346-350 - 2016
- [c60]Chun-Wei Chen, Fang-Kai Hsu, Der-Wei Yang, Jonas Wang, Ming-Der Shieh:
Effective model construction for enhanced prediction in example-based super-resolution. APCCAS 2016: 156-159 - [c59]Chun-Wei Chen, Fang-Kai Hsu, Der-Wei Yang, Jonas Wang, Ming-Der Shieh:
Fast model searching and combining for example learning-based super-resolution. ISCAS 2016: 1994-1997 - [c58]Ting-Yu Lin, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh:
Motion-Aware Iterative Closest Point Estimation for Fast Visual Odometry. ISMAR Adjunct 2016: 268-269 - [c57]Wen-Jie Chen, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh:
Effective Registration for Multiple Users AR System. ISMAR Adjunct 2016: 270-271 - 2015
- [j34]Der-Wei Yang, Li-Chia Chu, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh:
Depth-Reliability-Based Stereo-Matching Algorithm and Its VLSI Architecture Design. IEEE Trans. Circuits Syst. Video Technol. 25(6): 1038-1050 (2015) - [j33]Hsin-Fu Luo, Yi-Jun Liu, Ming-Der Shieh:
Efficient Memory-Addressing Algorithms for FFT Processor Design. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2162-2172 (2015) - [j32]Jing-Shiun Lin, Yin-Tsung Hwang, Shih-Hao Fang, Po-Han Chu, Ming-Der Shieh:
Low-Complexity High-Throughput QR Decomposition Design for MIMO Systems. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2342-2346 (2015) - [c56]Hsin-Fu Luo, Ming-Der Shieh:
Efficient memory management scheme for pipelined shared-memory FFT processors. ICCE-TW 2015: 178-179 - [c55]Hsin-Fu Luo, Ming-Der Shieh, Kun-Hsien Lee:
A radix-2/3/22/23 MDC architecture for variable-length FFT processors. ICCE-TW 2015: 180-181 - [c54]Chun-Wei Chen, Ching-Heng Su, Der-Wei Yang, Jonas Wang, Chia-Cheng Lo, Ming-Der Shieh:
High-quality texture compression using adaptive color grouping and selection algorithm. ISCAS 2015: 2760-2763 - [c53]Jing-Shiun Lin, Ming-Der Shieh, Chung-Yen Liu, Der-Wei Yang:
Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced. VLSI-DAT 2015: 1-4 - [c52]Shih-Hao Fang, Ju-Ya Chen, Jing-Shiun Lin, Ming-Der Shieh, Jen-Yuan Hsu:
Blind Channel Estimation for CP/CP-Free OFDM Systems Using Subspace Approach. VTC Spring 2015: 1-5 - 2014
- [j31]Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh:
Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement. IEEE Trans. Computers 63(2): 475-483 (2014) - [c51]Jheng-Hao Ye, Szu-Han Huang, Ming-Der Shieh:
An efficient countermeasure against power attacks for ECC over GF(p). ISCAS 2014: 814-817 - [c50]Yung-Kuei Lu, Shen-Ming Chung, Ming-Der Shieh:
Low-complexity architecture for Chase soft-decision Reed-Solomon decoding. VLSI-DAT 2014: 1-4 - [c49]Der-Wei Yang, Li-Chia Chu, Chun-Wei Chen, Jia-Ming Gan, Jonas Wang, Ming-Der Shieh:
Low complexity stereo matching algorithm using adaptive sized square window. VLSI-DAT 2014: 1-4 - [c48]Shih-Hao Fang, Ju-Ya Chen, Jing-Shiun Lin, Ming-Der Shieh, Jen-Yuan Hsu:
Subspace-Based Blind Channel Estimation for MIMO-OFDM Systems with New Signal Permutation Method. VTC Spring 2014: 1-5 - 2013
- [j30]Chia-Cheng Lo, Chia-Wei Hsu, Ming-Der Shieh:
Low-complexity multi-standard variable length coding decoder using tree-based partition and classification. IET Image Process. 7(3): 185-190 (2013) - [j29]Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin:
Subspace-Based Blind Channel Estimation by Separating Real and Imaginary Symbols for Cyclic-Prefixed Single-Carrier Systems. IEEE Trans. Broadcast. 59(4): 698-704 (2013) - [j28]Shanthi Pavan, Wouter A. Serdijn, Henry Shu-Hung Chung, Ming-Der Shieh, Young Hwan Kim:
Guest Editorial Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012). IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1101-1103 (2013) - [j27]Yung-Fa Chou, Ding-Ming Kwai, Ming-Der Shieh, Cheng-Wen Wu
Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2343-2351 (2013) - [c47]Jheng-Hao Ye, Tsung-Wei Hung, Ming-Der Shieh:
Energy-efficient architecture for word-based Montgomery modular multiplication algorithm. VLSI-DAT 2013: 1-4 - [c46]Shih-Hao Fang, Ju-Ya Chen, Jing-Shiun Lin, Ming-Der Shieh, Dung-Rung Hsieh, Jen-Yuan Hsu:
Subspace-Based Blind Channel Estimation for MIMO-OFDM Systems with Repetition Index. VTC Fall 2013: 1-5 - 2012
- [j26]Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang:
Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders. IEICE Trans. Inf. Syst. 95-D(2): 549-557 (2012) - [j25]Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin:
Blind channel estimation for cyclic prefix-free orthogonal frequency-division multiplexing systems with particular input symbols. IET Commun. 6(16): 2654-2660 (2012) - [j24]Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon
Implementations of Signal-Processing Algorithms for OFDM Systems. J. Electr. Comput. Eng. 2012: 687172:1-687172:2 (2012) - [c45]Shih-Hao Fang, Ju-Ya Chen, Jing-Shiun Lin, Ming-Der Shieh, Wei-Chieh Huang, Jen-Yuan Hsu:
Blind channel estimation for MIMO-OFDM systems with repeated time-domain symbols. APCCAS 2012: 37-40 - [c44]Der-Wei Yang, Chun-Wei Chen, Che-Hao Chang, Yun-Chen Chang, Ming-Der Shieh, Jonas Wang, Chia-Cheng Lo:
Face detection architecture design using hybrid skin color detection and cascade of classifiers. APCCAS 2012: 543-546 - [c43]Der-Wei Yang, Jing-Shiun Lin, Shih-Hao Fang, Chia-Fen Lin, Ming-Der Shieh:
High-performance turbo-MIMO system design with iterative soft-detection and decoding. APSIPA 2012: 1-4 - [c42]Shen-Ming Chung, Ming-Der Shieh, Lung-Chih Kuo, Hsiao-Hui Lee:
A low-latency turbo decoding scheme for diversities-based communication systems. ICSPCS 2012: 1-6 - [c41]Wen-Ching Lin, Jheng-Hao Ye, Der-Wei Yang, Si-Yu Huang, Ming-Der Shieh, Jonas Wang:
Efficient scissoring scheme for scanline-based rendering of 2D vector graphics. ISCAS 2012: 766-769 - [c40]Jing-Shiun Lin, Yin-Tsung Hwang, Po-Han Chu, Ming-Der Shieh, Shih-Hao Fang:
An efficient QR decomposition design for MIMO systems. ISCAS 2012: 1508-1511 - [c39]Sheng-Hong Wang, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh:
Fast scalable radix-4 Montgomery modular multiplier. ISCAS 2012: 3049-3052 - [c38]Yung-Kuei Lu, Ming-Der Shieh:
Efficient architecture for Reed-Solomon decoder. VLSI-DAT 2012: 1-4 - 2011
- [j23]Chin-Long Wey, Shin-Yo Lin, Pei-Yun Tsai, Ming-Der Shieh:
Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(7): 1530-1539 (2011) - [j22]Ming-Der Shieh, Yung-Kuei Lu:
Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems. IEICE Trans. Inf. Syst. 94-D(8): 1557-1564 (2011) - [j21]Ming-Der Shieh, Wen-Ching Lin, Chien-Ming Wu:
Design of High-Speed Iterative Dividers in GF(2m). J. Inf. Sci. Eng. 27(3): 953-967 (2011) - [c37]Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang:
VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes. SoCC 2011: 242-246 - 2010
- [j20]Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin:
Blind Channel Estimation for SIMO-OFDM Systems without Cyclic Prefix. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(1): 339-343 (2010) - [j19]Yung-Kuei Lu, Ming-Der Shieh:
High-Speed Low-Complexity Architecture for Reed-Solomon Decoders. IEICE Trans. Inf. Syst. 93-D(7): 1824-1831 (2010) - [j18]Ming-Der Shieh, Wen-Ching Lin:
Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures. IEEE Trans. Computers 59(8): 1145-1151 (2010) - [j17]Chia-Cheng Lo, Shang-Ta Tsai, Ming-Der Shieh:
Reconfigurable architecture for entropy decoding and inverse transform in H.264. IEEE Trans. Consumer Electron. 56(3): 1670-1676 (2010) - [j16]Shin-Yo Lin, Chin-Long Wey, Ming-Der Shieh:
Low-cost FFT processor for DVB-T2 applications. IEEE Trans. Consumer Electron. 56(4): 2072-2079 (2010) - [j15]Jun-Hong Chen, Ming-Der Shieh, Wen-Ching Lin:
A High-Performance Unified-Field Reconfigurable Cryptographic Processor. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1145-1158 (2010) - [c36]Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin:
A signal permutation method for cyclic-prefix-free OFDM channel estimation. APCCAS 2010: 656-659 - [c35]Der-Wei Yang, Ming-Der Shieh, Wen-Hsuen Kuo, Jonas Wang:
Efficient protocol converter generation for system integration. APCCAS 2010: 903-906 - [c34]Chia-Cheng Lo, Chia-Wei Hsu, Ming-Der Shieh:
Area-Efficient H.264 VLC Decoder Using Sub-tree Classification. IIH-MSP 2010: 284-287 - [c33]Wen-Ching Lin, Ming-Der Shieh, Chien-Ming Wu:
Design of high-speed bit-serial divider in GF(2m). ISCAS 2010: 713-716 - [c32]Hsin-Fu Luo, Ming-Der Shieh, Yi-Jun Liu, Chien-Ming Wu:
Efficient memory management for FFT processors. ISCAS 2010: 3737-3740 - [c31]Yung-Kuei Lu, Ming-Der Shieh, Chien-Ming Wu:
Low-complexity Reed-Solomon decoder for optical communications. ISCAS 2010: 4173-4176 - [c30]Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin:
Subspace-Based Blind Channel Estimation for OFDM Systems with Conjugate-Symmetric Property. VTC Spring 2010: 1-5
2000 – 2009
- 2009
- [j14]Chia-Cheng Lo, Ying-Jhong Zeng, Ming-Der Shieh:
Design of a High-Throughput CABAC Encoder. IEICE Trans. Inf. Syst. 92-D(4): 681-688 (2009) - [j13]Ming-Der Shieh, Tai-Ping Wang, Der-Wei Yang:
Low-power register-exchange survivor memory architectures for Viterbi decoders. IET Circuits Devices Syst. 3(2): 83-90 (2009) - [j12]Ming-Der Shieh, Jun-Hong Chen, Wen-Ching Lin, Chien-Ming Wu:
An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m). J. Inf. Sci. Eng. 25(5): 1555-1573 (2009) - [j11]Ming-Der Shieh, Jun-Hong Chen, Wen-Ching Lin, Hao-Hsuan Wu:
A New Algorithm for High-Speed Modular Multiplication Design. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2009-2019 (2009) - [c29]Chia-Cheng Lo, Jung-Guan Luo, Ming-Der Shieh:
Hardware/Software Codesign of Resource Constrained Real-Time Systems. IAS 2009: 177-180 - [c28]Jun-Jie Zhu, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh:
Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors. Asian Test Symposium 2009: 206-211 - [c27]Wen-Ching Lin, Ming-Der Shieh, Chien-Ming Wu:
Flexible GF(2m) Divider Design for Cryptographic Applications. ISCAS 2009: 25-28 - [c26]Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin:
A Generalized Blind Channel Estimation Algorithm for OFDM Systems with Cyclic Prefix. ISCAS 2009: 2469-2472 - [c25]Shih-Hao Fang, Ju-Ya Chen, Ming-Der Shieh, Jing-Shiun Lin:
Modified Subspace Based Channel Estimation Algorithm for OFDM Systems. VTC Spring 2009 - 2008
- [j10]Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu:
Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders. IEICE Trans. Inf. Syst. 91-D(9): 2300-2311 (2008) - [j9]Chin-Long Wey, Ming-Der Shieh, Shin-Yo Lin:
Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3430-3437 (2008) - [j8]Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin:
A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1151-1161 (2008) - [c24]Wei-Chang Tsai, Ming-Der Shieh, Wen-Ching Lin, Chin-Long Wey:
Design of square generator with small look-up table. APCCAS 2008: 172-175 - [c23]Jun-Hong Chen, Sue-Jing Huang, Wen-Ching Lin, Yung-Kuei Lu, Ming-Der Shieh:
Exploration of Low-Cost Configurable S-Box Designs for AES Applications. ICESS 2008: 422-428 - [c22]Wen-Ching Lin, Jun-Hong Chen, Ming-Der Shieh:
A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m). ISCAS 2008: 464-467 - [c21]Jun-Hong Chen, Wen-Ching Lin, Hao-Hsuan Wu, Ming-Der Shieh:
High-speed modular multiplication design for public-key cryptosystems. ISCAS 2008: 680-683 - 2007
- [c20]Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin:
A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem. ISCAS 2007: 3780-3783 - 2006
- [j7]Ming-Der Shieh, Jun-Hong Chen, Chien-Ming Wu:
High-Speed Design of Montgomery Inverse Algorithm over GF(2m). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 559-565 (2006) - [c19]Jun-Hong Chen, Ming-Der Shieh, Haw-Shiuan Wu, Wen-Ching Lin:
Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation. APCCAS 2006: 606-609 - [c18]Jing-Shiun Lin, Chung-Kung Lee, Ming-Der Shieh, Jun-Hong Chen:
High-speed CRC design for 10 Gbps applications. ISCAS 2006 - [c17]Ming-Der Shieh, Yung-Kuei Lu, Shen-Ming Chung, Jun-Hong Chen:
Design and implementation of efficient Reed-Solomon decoders for multi-mode applications. ISCAS 2006 - [c16]Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang:
Efficient path metric access for reducing interconnect overhead in Viterbi decoders. ISCAS 2006 - 2005
- [j6]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen:
VLSI architectural design tradeoffs for sliding-window log-MAP decoders. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 439-447 (2005) - [c15]Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu:
Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. ISCAS (5) 2005: 5254-5257 - 2004
- [j5]Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). IEEE Trans. Computers 53(3): 375-380 (2004) - [c14]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo:
VLSI architecture exploration for sliding-window Log-MAP decoders. ISCAS (2) 2004: 513-516 - 2003
- [c13]Chien-Ming Wu, Ming-Der Shieh, Hsin-Fu Lo, Min-Hsiung Hu:
Implementation of channel demodulator for DAB system. ISCAS (2) 2003: 137-140 - 2002
- [j4]Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Novel Algorithms and VLSI Design for Division over GF(2m). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(5): 1129-1139 (2002) - [c12]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu:
Memory arrangements in turbo decoders using sliding-window BCJR algorithm. ISCAS (5) 2002: 557-560 - [c11]Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
An area-efficient systolic division circuit over GF(2m) for secure communication. ISCAS (5) 2002: 733-736 - 2001
- [j3]Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo:
A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17(3): 445-461 (2001) - [c10]Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) 2001: 33-36 - [c9]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) 2001: 206-209 - [c8]Ming-Hwa Sheu, Ho-En Liao, Shih Tsung Kan, Ming-Der Shieh:
A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. ISCAS (4) 2001: 446-449 - [c7]Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu:
Design of an efficient FFT processor for DAB system. ISCAS (4) 2001: 654-657 - 2000
- [c6]Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu:
High-speed generation of LFSR signatures. Asian Test Symposium 2000: 222- - [c5]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
An efficient approach for in-place scheduling of path metric update in Viterbi decoders. ISCAS 2000: 61-64
1990 – 1999
- 1999
- [j2]Ming-Der Shieh, Chien-Ming Wu, Hsiao-Hsing Chou, Min-Hui Chen, Chia-Liang Liu:
Design and implementation of a DAB channel decoder. IEEE Trans. Consumer Electron. 45(3): 553-562 (1999) - [c4]Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu:
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ISCAS (1) 1999: 500-503 - [c3]Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu:
An area-efficient versatile Reed-Solomon decoder for ADSL. ISCAS (1) 1999: 517-520 - 1998
- [j1]Chin-Long Wey, Ming-Der Shieh:
Design of a High-Speed Square Generator. IEEE Trans. Computers 47(9): 1021-1026 (1998) - 1996
- [c2]Chie Dou, Ming-Der Shieh:
A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management. ICCD 1996: 149-152 - 1993
- [c1]Chin-Long Wey, Ming-Der Shieh, P. David Fisher:
ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits. ICCD 1993: 159-162
Coauthor Index
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last updated on 2024-10-30 20:30 CET by the dblp team
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