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ISOCC 2012: Jeju, South Korea
- International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012. IEEE 2012, ISBN 978-1-4673-2989-7
- Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang:
A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems. 1-4 - Kwang-Ho Kim, Bai-Sun Kong, Young-Hyun Jun:
Adaptive frequency-controlled ultra-fast hysteretic buck converter for portable devices. 5-8 - Keon Lee, Dong-hun Lee, Su-hun Yang, Ji-hyun Park, Kwang Sub Yoon:
Design of high dimming ratio power-LED driver with preloading inductor current methodology. 9-12 - Yanan Sun, Volkan Kursun
:
NP dynamic CMOS resurrection with carbon nanotube field effect transistors. 13-16 - Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara:
A novel charge recovery logic structure with complementary pass-transistor network. 17-20 - Yunlong Zhang, Qiang Tong, Li Li, Wei Wang, Ken Choi, JongEun Jang, Hyobin Jung, Si-Young Ahn:
Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes. 21-24 - Jae-Jin Lee, Kyungjin Byun, Nak-Woong Eum:
Multi-core architecture for video decoding. 25-28 - Po-Kuan Huang, Tung-Yang Lin, Hsu-Ting Lin, Chi-Hao Wu, Ching-Chun Hsiao, Chao-Kang Liao, Peter Lemmens:
Real-time stereo matching for 3D hand gesture recognition. 29-32 - Chae-Eun Rhee, Hyun Kim, Hyuk-Jae Lee:
An inter-frame macroblock schedule for memory access reduction in H.264/AVC bi-directional prediction. 33-36 - Chan Young Jang, Jae Hwan Lim, Young Hwan Kim:
A fast Multi-scale Retinex algorithm using dominant SSR in weights selection. 37-40 - Pramila Welling, Sung Hoon Kim, Sang-Bock Cho:
Brightness preserving contrast enhancement using polynomial histogram amendment. 41-44 - Soojin Kim, Seonyoung Lee, Kyeongsoon Cho:
Design of high-speed support vector machine circuit for driver assistance system. 45-48 - Woo-Rham Bae
Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface. 49-52 - Taeho Kim, Deog-Kyoon Jeong:
A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology. 53-56 - Oleksiy Klymenko, Denys I. Martynenko, Gunter Fischer:
A highly integrated IR-UWB transceiver for communication and localization. 57-60 - Debashis Dhar, Inhwa Jung, Chulwoo Kim:
A TDC-based skew compensation technique for high-speed output driver. 61-64 - Jeong-Min Lee, Woo-Young Choi, Holger Rücker:
60-GHz voltage-controlled oscillator and frequency divider in 0.25-µm SiGe BiCMOS technology. 65-67 - Young-Ho Choi, Jae-Yoon Sim, Hong-June Park:
A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator. 68-71 - Bingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao:
Contention and energy aware mapping for real-time applications on Network-on-Chip. 72-76 - Kazutoshi Kodama, Makoto Ikeda:
Target voltage independent capacitance measurement circuit implemented by 0.18 µm CMOS for PWM-MEMS control. 77-80 - Younghwan Yun, Myoungsun Kim:
A WDR method with low noise in digital circuit. 81-83 - Zhongyun Yuan, Jun Dong Cho
Redundant-dictionary based adaptive sampling for transient ECG signal measurement. 84-87 - Siddharth Katare, Narayanan Natarajan:
Current equalization scheme for parallel low-dropout regulators. 88-91 - Ning Ren, Hao Zhang, Tsutomu Yoshihara:
A CMOS voltage reference combining body effect with switched-current technique. 92-95 - Shafqat Ali, Steve Tanner, Pierre-André Farine:
Design and analysis of a power-efficient cascode-compensated amplifier. 96-99 - Debashis Mandal, Pradip Mandal, Tarun Kanti Bhattacharyya
Spur suppression in frequency synthesizer using switched capacitor array. 100-103 - Jinsoo Rhim, Kwang-Chun Choi, Woo-Young Choi:
A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology. 104-107 - Jae-Hyeon Shin, Kang-Il Cho, Gil-Cho Ahn:
A digitally enhanced low-distortion delta-sigma modulator for wideband application. 108-111 - Tommy Halim, Karsten Leitis:
Digitizing the feedback signal in a magnetic field (AMR) sensor system using delta sigma modulator topology. 112-115 - Hung-Wen Lin, Hsin-Lin Hu, Wu-Wei Lin:
A DLL-based FSK demodulator for 5.8GHz DSRC/ETC RF receiver. 116-119 - Igors Homjakovs, Masanori Hashimoto
Signal-dependent analog-to-digital converter based on MINIMAX sampling. 120-123 - Sang-Pil Nam, Yongmin Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee:
A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications. 124-127 - Sungken Lee, Geontae Park, Hyungtak Kim
A programmable delay-locked loop based clock multiplier. 128-130 - Yeonseong Hwang, Jangwoo Lee, Daeyun Kim, Minkyu Song:
A wide dynamic range CMOS image sensor based on a new gamma correction technique. 131-134 - Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa
Energy-efficient high-level synthesis for HDR architectures with clock gating. 135-138 - Mitsuya Uchida, Ittetsu Taniguchi
Energy-aware SA-based instruction scheduling for fine-grained power-gated VLIW processors. 139-142 - Sangdo Park, Taewhan Kim:
Die matching algorithm for enhancing parametric yield of 3D ICs. 143-146 - Chungki Oh, Hyung-Ock Kim, Jun Seomun, Wook Kim, Jaehan Jeon, Kyung Tae Do, Hyo-Sig Won, Kee Sup Kim:
Thermal-aware body bias modulation for high performance mobile core. 147-150 - Rahim Soleymanpour, Siamak Mohammadi
A synthesis algorithm for customized heterogeneous multi-processors. 151-154 - Yuta Atobe, Youhua Shi
Dynamically changeable secure scan architecture against scan-based side channel attack. 155-158 - Dongwoo Lee
A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem. 159-162 - Amit Kumar, Sudhakar M. Reddy, Bernd Becker
Performance aware partitioning for 3D-SOCs. 163-166 - Mohamed A. Abd El-Ghany
Hybrid Mesh-Ring wireless Network on Chip for multi-core system. 167-170 - Sangchul Kim, Hyunjin Kim, Taeil Chung, Jin-Gyeong Kim:
Design of H.264 video encoder with C to RTL design tool. 171-174 - Zhaohui Hu, Arnaud Pierres, Shiqing Hu, Chen Fang, Philippe Royannez, Eng Pek See, Yean Ling Hoon:
Practical and efficient SOC verification flow by reusing IP testcase and testbench. 175-178 - Shao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong
Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure. 179-184 - Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyungho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang:
Integration of dual channel timing formatter system for high speed memory test equipment. 185-187 - Ching-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, Chun-Yao Wang:
Error Injection & Correction: An efficient formal logic restructuring algorithm. 188-191 - Il-Min Yi, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park:
An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits. 192-195 - Weijie Cheng, Jeong-Wook Cho, Yeonbae Chung:
Design of logic-compatible embedded DRAM using gain memory cell. 196-199 - Zhao Chuan Lee, Kim Ming Ho, Zhi-Hui Kong, Tony T. Kim:
NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells. 200-203 - Junya Kaida, Takuji Hieda, Ittetsu Taniguchi
Task mapping techniques for embedded many-core SoCs. 204-207 - Shinwon Lee, V. Meka, Mingu Jeon, Nagoo Sung, Jeongnam Youn:
Dynamic load balancing algorithm for system on chip. 208-211 - Seung-Kwon Lee, In-Ho Kook, Jin-Hyeung Kong:
A study of mobile Optical Image Stabilization system for mobile camera. 212-214 - Yongmin Jung
7.7Gbps encoder design for IEEE 802.11n/ac QC-LDPC codes. 215-218 - Byung Jun Choi, Jae Do Lee, Myung Hoon Sunwoo, Xinmiao Zhang:
Low complexity full parallel Multi-Split LDPC decoder reusing sign wire of row processor. 219-222 - Hoyoung Yoo
Low-latency area-efficient decoding architecture for shortened reed-solomon codes. 223-226 - Jihyun Ryoo, Seuk Son, Jaeha Kim:
Design of low-power high-radix switch fabric with partially-activated input and output lines. 227-230 - In-Gul Jang, Dae-Ho Kim, Ho-Yun Yi, Jin-Gyun Chung, Kyung-Ju Cho:
Efficient IFFT architecture design for OFDM applications. 231-234 - Yoshichika Fujioka, Michitaka Kameyama:
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. 235-238 - Tso-Bing Juang, Hsin-Hao Peng, Han-Lung Kuo:
Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders. 239-242 - Fahian Ahmed, Byeong Kil Lee, Bum Joo Shin, Duk Soo Son, Young Choon Woo, Wan Choi:
Performance hotspot based CUDA acceleration. 243-246 - Byung-Min Lee, Gi-Ho Park:
Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM. 247-250 - Dong-Hyun Kim, Jongwon Yun
Si-based D-band frequency conversion circuits. 251-253 - Ruonan Han, Yaming Zhang, Youngwan Kim, Dae Yeon Kim, Hisashi Shichijo, Kenneth K. O:
Terahertz image sensors using CMOS Schottky barrier diodes. 254-257 - Kun-You Lin
Development of millimeter-wave CMOS power amplifiers at National Taiwan University. 258-261 - Jae-Young Kim, Ho-Jin Song
InP HBT voltage controlled oscillator for 300-GHz-band wireless communications. 262-265 - Holger Rücker, Bernd Heinemann:
SiGe BiCMOS technology for mm-wave systems. 266-268 - Eng Gee Lim
Transmitter antennas for wireless capsule endoscopy. 269-272 - Danny Hughes, Ka Lok Man, Zhun Shen, Kyung Ki Kim:
A loosely-coupled binding model for Wireless Sensor Networks. 273-276 - Sanaz Rahimi Moosavi
An efficient history-based routing algorithm for interconnection networks. 277-280 - Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila
Partial-LastZ: An optimized hybridization technique for 3D NoC architecture enabling adaptive inter-layer communication. 281-284 - Zhun Shen, Ka Lok Man, Chi-Un Lei
Assuring system reliability in wireless sensor networks via verification and validation. 285-288 - Enle Chen, Yun Chen, Yizhi Wang, Chen Chen, Xiaoyang Zeng:
A multi-core mapping implementation of 3780-point FFT. 289-292 - Tsuyoshi Isshiki, Hao Xiao, Hsuan-Chun Liao, Dongju Li, Hiroaki Kunieda:
Application-specific Instruction-Set Processor design methodology for wireless image transmission systems. 293-296 - Hongbin Sun, Longjun Liu
Design and implementation of a video display processing SoC for full HD LCD TV. 297-300 - Yan Zhao, Qingqing Yang, Xiaofang Zhou, Nianrong Zhou, Yufeng Cui:
A smart platform with cognitive techniques for narrowband power line communication. 301-304 - Licai Fang, Qinghua Guo
A low cost soft mapper for turbo equalization with high order modulation. 305-308 - Tae-Yon Lee, Jung-Kyu Jung, Dong-Ki Min, Yoondong Park, Kwanghyuk Bae, Tae-Chan Kim:
Perspectives on 3D ToF sensor SoC integration for user interface application. 309-312 - Youngjin Kim, Sungkwang Cho, Byungjoon Back, Taechan Kim:
Face detection based on chrominance and luminance for simple design. 313-316 - Manlyun Ha, Sun Choi, DongHun Cho, Hosoo Kim, Jungyeon Cho, Youngsun Oh, Jongman Kim, Sangwon Yoon, Changhoon Choi, Juneseok Lee, Juil Lee, Joon Hwang:
Sensitivity improvement in FSI CIS using the M1ToP™ smart process technique. 317-319 - Minkyu Kang, Hoon Jang, Sunjae Hwang, Soeun Park, Sanghwa Kim, Hosoon Ko, Changhun Han, Joon Hwang:
Pixel design and photodiode process technology for image sensor applications. 320-323 - Shubham Mittal, Twisha Prasad, Suraj Saurabh, Xue Fan, Hyunchul Shin:
Pedestrian detection and tracking using deformable part models and Kalman filtering. 324-327 - Alexander Getman, Se-Hwan Yun, Tae-Chan Kim:
Improved nonlocal means denoising for images with tone gradients. 328-331 - Yun Chen, Yuebin Huang, Wei Meng, Zhiyi Yu, Xiaoyang Zeng:
A low-cost architecture for multi-mode Reed-Solomon decoder. 332-334 - Jen-Yu Hou, Tsao-Shuan Lee, Pei-Yun Tsai:
High-throughput turbo decoder design with new interconnection network for LTE/LTE-A system. 335-338 - Leixin Zhou, Jin Sha, Zhongfeng Wang:
Efficient EMS decoding for non-binary LDPC codes. 339-342 - Chi-Hsuan Hsieh, Ming-Yong Lee, Yuan-Hao Huang:
A 516Mb/s 0.2nJ/bit/iter variable-block-size turbo decoder for 3GPP LTE-A system. 343-346 - Yeong-Luh Ueng
A study into high-throughput decoder architectures for high-rate LDPC codes. 347-350 - Haiqing Nan, Wei Wang, Ken Choi:
Circuit design for carbon nanotube field effect transistors. 351-354 - Krishna Rao Vijayanagar, Maziar Loghman, Joohee Kim:
Refinement of depth maps generated by low-cost depth sensors. 355-358 - Hoi-Jin Lee, Youngmin Shin, Jae Cheol Son, Tae Hee Han, Bai-Sun Kong:
An efficient dual-supply design for low-power mobile systems. 359-362 - Jun Hoe Heo, Jong-Hak Kim, Dong-Hun Lee, Yong-Han Kim, Jun Dong Cho
Real-time digital image stabilization using motion sensors for search range reduction. 363-366 - Tony T. Kim, Bo Wang
High energy efficient ultra-low voltage SRAM design: Device, circuit, and architecture. 367-370 - Di Zhu, Qi Huang, Zhao Chuan Lee, Yuanjin Zheng, Liter Siek
A novel analog-to-residue converter for biomedical DSP application. 371-374 - Arup K. George
CMOS-MEMS capacitive sensors for intra-cranial pressure monitoring: Sensor fabrication & system design. 375-378 - Zhong Qiang Ding, Kiat Seng Yeo
An optimum RF link for implantable devices with rectification of transmission errors. 379-382 - Haitao Wang, Kiat Seng Yeo, Anh-Tuan Do, Yung Sern Tan, Kai Kang, Zhenghao Lu:
A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor. 383-386 - Anh-Tuan Do, Yung Sern Tan, Chun Kit Lam, Minkyu Je, Kiat Seng Yeo
Low power implantable neural recording front-end. 387-390 - Youngchan Lee, Namdo Kim, Jay B. Kim, Byeong Min:
Millions to thousands issues through knowledge based SoC CDC verification. 391-394 - DaeSeo Cha, HyunWoo Koh, NamPhil Jo, Jay B. Kim, Byeong Min, Karthik Kothandapani, Riccardo Oddone, Adam D. Sherer:
Verification of massive advanced node SoCs. 395-397 - Yeon-Ho Im, Seong-Hee Yim, Jay B. Kim:
A web service for automated IP/SoC verification using computers on network. 398-401 - Kyuho Shim, Woojoo Kim
System-level simulation acceleration for architectural performance analysis using hybrid virtual platform system. 402-404 - Namdo Kim, Young-Nam Yun, Young-Rae Cho, Jay B. Kim, Byeong Min:
How to automate millions lines of top-level UVM testbench and handle huge register classes. 405-407 - Sung-Pah Lee, Kunhee Cho, Minwoo Lee, Wookang Jin:
A leakage reduced HVIC with coarse-fine UVLO. 408-411 - Lei Sun, Kong-Pang Pun:
Low-offset comparator using capacitive self-calibration. 412-414 - Jae-Hyoun Park, Hyung-Do Yoon:
Design of LED driver using digital up/down counter. 415-418 - Jin-Cheol Seo, Tae-Ho Kim, Taek-Joon An, Kwan Yoon, Jin-Ku Kang:
A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern. 419-422 - Seung-Wook Oh, Hyung-Min Park, Joon-Hyup Seo, Jae-Young Jang, Gi-Yeol Bae, Jin-Ku Kang:
A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS. 423-426 - Shafqat Ali, Steve Tanner, Pierre-André Farine:
A background calibration method for DAC mismatch correction in multibit sigma-delta modulators. 427-430 - Minsoo Kang, Jinwook Burm:
Time-domain temperature sensor using two stage vernier type time to digital converter for mobile application. 431-434 - Edward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim:
A design and integration of Parametric Measurement Unit on to a 600MHz DCL. 435-438 - Kuang-Hao Lin, Tai-Hsuan Yang, Jan-Dong Tseng:
A low power CMOS receiver front-end for long term evolution systems. 439-442 - Chih-Hung Lin, Robert Chen-Hao Chang
A low-complexity bio-medical signal receiver for wireless body area network. 443-446 - Sehoon Yoo, Sehyun Song, Kichul Kim, Chanwoo Park, Jungchul Gong:
Multi-function unit for LED lighting. 447-450 - Jeong-In Park, Jewong Yeon, Seung-Jun Yang, Hanho Lee:
An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture. 451-454 - Sanghoon Park, Kwang-Ho Ahn, Ki-Jin Kim:
An 880 / 1760 MHz tunable bandwidth active RC low-pass filter using high gain amplifier. 455-457 - Sharad Gupta, Parvinder Kumar Rana:
A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit. 458-461 - Gun Sang Park, Hyun Jin Choi, Nagakarthik Tumuganti, Jun Rim Choi:
Verification of an efficient Match-line Sense Amplifier for the High Frequency Search Operation. 462-465 - Hailong Jiao, Volkan Kursun
Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits. 466-469 - Anis Feki, Bruno Allard, David Turgis, Jean-Christophe Lafont, Lorenzo Ciampolini:
Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell. 470-474 - Woojin Yun, Jongpil Jung, Kyungsu Kang, Chong-Min Kyung:
Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFS. 475-478 - Junha Lee, Hanwool Jeong, Younghwi Yang, Jisu Kim, Seong-Ook Jung:
Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM. 479-482 - Luchen Yu, Yuan Zhu
High efficiency multi-channel LED driver based on SIMO switch-mode converter. 483-486 - Xuan-Dien Do, Seok-Kyun Han, Sang-Gug Lee:
Low power consumption for detecting current zero of synchronous DC-DC buck converter. 487-490 - Taeyoung Lee, Cheul-Hee Hahm, Gunyoung Bae, Byunghoan Chon, Kangwook Chun:
An efficient JPEG decoding and scaling method for digital TV platforms. 491-493 - Jung-yong Lee, Hoon Heo, Kwang-Yeob Lee, Yong-Seo Koo:
Design of multi-core rasterizer for parallel processing. 494-497 - Minsu Choi, Jinsang Kim, Ik Joon Chang, Won-Kyung Cho:
Low-complexity frame scheduler using shared frame memory for multi-view video coding. 498-502 - Su-hyun Lee, Yong-Jin Jeong:
Development of a verification platform for intelligent surveillance camera systems. 503-505 - Dajun Ding, Jihwan Yoon, Chanho Lee:
Traffic sign detection and identification using SURF algorithm and GPGPU. 506-508 - Hi-Seok Kim, Sea-Ho Kim, Won-Ki Go, Sang-Bock Cho:
FPGA implementation of stereoscopic image proceesing architecture base on the gray-scale projection. 509-512 - Young-Kyun Park, Ji-Hoon Lim, Jae-Kyung Wee, Inchae Song:
One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique. 513-516
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