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Jin-Ku Kang
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2020 – today
- 2024
- [j34]Hyunjun Ko
, Jin-Ku Kang
Adaptive Scaling Filter Pruning Method for Vision Networks With Embedded Devices. IEEE Access 12: 123771-123781 (2024) - [j33]Jin-Ho Kim
1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4061-4065 (2024) - [j32]Jaemyung Kim
MASCAR: Multidomain Adaptive Spatial-Spectral Variable Compression Artifact Removal Network for Multispectral Remote Sensing Images. IEEE Trans. Geosci. Remote. Sens. 62: 1-20 (2024) - [c35]Hyunjun Ko, Jin-Ku Kang, Yongwoo Kim:
An Efficient and Fast Filter Pruning Method for Object Detection in Embedded Systems. AICAS 2024: 204-207 - [c34]Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim:
Fast, Efficient and Lightweight Compressed Image Super-Resolution Network for Edge Devices. AICAS 2024: 352-356 - 2023
- [j31]Yong-Sung Ahn, Jeong-Mi Park, Jin-Ku Kang
A ±0.48°C (3σ) Inaccuracy BJT-Based Temperature Sensor With 241 μs Conversion Time for Display Driver IC in 40 nm CMOS. IEEE Access 11: 132843-132851 (2023) - [c33]Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim:
An FPGA-based Lightweight Deblocking CNN for Edge Devices. ISCAS 2023: 1-5 - [c32]Seoung-Geun Cho, Jin-Ku Kang:
A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler. ISOCC 2023: 115-116 - [c31]Jeong-Mi Park, Jin-Ku Kang:
A PAM-4 Receiver with Selective Reference Voltage Adaptation for Low Sensitivity to Sampler Voltage Variations. ISOCC 2023: 205-206 - 2022
- [j30]Jaepil Bak
An Overhead-Reduced Key Coding Technique for High-Speed Serial Interface. IEEE Access 10: 21187-21192 (2022) - [j29]Jihun Jeon
Target Capacity Filter Pruning Method for Optimized Inference Time Based on YOLOv5 in Embedded Systems. IEEE Access 10: 70840-70849 (2022) - [j28]Jaemyung Kim
A Low-Cost Fully Integer-Based CNN Accelerator on FPGA for Real-Time Traffic Sign Recognition. IEEE Access 10: 84626-84634 (2022) - [c30]Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim:
An FPGA Implementation of CNN-based Compression Artifact Reduction. ISOCC 2022: 95-96 - [c29]Hyun-In Kim, Jin-Ku Kang:
A Low-Power Counter-based Digital CDR. ISOCC 2022: 143-144 - [c28]Jin-Ho Kim, Jin-Ku Kang:
A Wide-range Low Power Quarter Rate Single Loop CDR. ISOCC 2022: 145-146 - [c27]Hwan-Ung Kim, Jin-Ku Kang:
High-speed Serial Interface using PWAM Signaling Scheme. ISOCC 2022: 255-256 - [c26]Sang-Ung Shin, Jin-Ku Kang, Yongwoo Kim:
A Design and Implementation of MIPI A-PHY RTS Layer. ISOCC 2022: 326-327 - [c25]Jihun Jeon, Jin-Ku Kang, Yongwoo Kim:
Filter Pruning Method for Inference Time Acceleration Based on YOLOX in Edge Device. ISOCC 2022: 354-355 - 2021
- [j27]Jaemyung Kim
A Resource Efficient Integer-Arithmetic-Only FPGA-Based CNN Accelerator for Real-Time Facial Emotion Recognition. IEEE Access 9: 104367-104381 (2021) - [j26]Nguyen Huu Tho
A 0.32-2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2347-2351 (2021) - [c24]Hyung-Wook Lee, Kyeong-Min Ko, Jin-Ku Kang:
An 8 - 26 Gb/s Single Loop Reference-less CDR with Unrestricted Frequency Acquisition. ISOCC 2021: 45-46 - [c23]Chang han Rho, Jin-Ku Kang, Jin Liu:
Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit. ISOCC 2021: 333-334 - [c22]Kyeong-Min Ko, Dohyeon Kwon, Jin-Ku Kang:
Design of 20Gb/s PAM4 Transmitter with Maximum Transition Elimination and Transition Compensation Techniques. ISOCC 2021: 405-406 - 2020
- [j25]Kyung-Sub Son
A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition. IEEE Trans. Circuits Syst. II Express Briefs 67-II(6): 974-978 (2020)
2010 – 2019
- 2019
- [j24]Seong-Mun An, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang:
Design of a third-order delta-sigma TDC with error-feedback structure. IEICE Electron. Express 16(3): 20181064 (2019) - [j23]Kyung-Sub Son, Yong-Hwan Moon, Sanghun Baek, Namyong Kim, Taek-Joon An, Jin-Ku Kang:
Eye-open monitor using two-dimensional counter value profile. IEICE Electron. Express 16(21): 20190601 (2019) - [j22]Yong-Hwan Moon, Jae-Wook Yoo
A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2907-2920 (2019) - 2018
- [c21]Min Kim, Kyung-Sub Son, Namhoon Kim, Chang Hang Rho, Jin-Ku Kang:
A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. ISOCC 2018: 143-144 - 2017
- [j21]Nguyen Huu Tho, Kyung-Sub Son, Jin-Ku Kang:
A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector. IEICE Electron. Express 14(8): 20161279 (2017) - 2016
- [j20]Bum-Hee Choi, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang:
A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's. IEICE Electron. Express 13(24): 20161086 (2016) - [c20]Bum-Hee Choi, Kyung-Sub Son, Jin-Ku Kang:
A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's. APCCAS 2016: 344-347 - [c19]Nguyen Huu Tho, Kyung-Sub Son, Kyongsu Lee
A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector. ISOCC 2016: 259-260 - 2015
- [j19]Kyung-Sub Son, Jin-Ku Kang:
On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR. IEICE Electron. Express 12(15): 20150570 (2015) - [j18]In-Seok Kong, Kyung-Sub Son, Kyongsu Lee
Precise time-difference repetition for TDC with delay mismatch cancelling scheme. IEICE Electron. Express 12(21): 20150752 (2015) - [j17]Hyun-Bae Jin, Gi-Yeol Bae, Kwang-Hee Yoon, Tae-Ho Kim, Ji-Hoon Jang, Byung Cheol Song, Jin-Ku Kang:
A Link Layer Design for DisplayPort Interface with State Machine Based Packet Processing. J. Signal Process. Syst. 79(1): 89-98 (2015) - [c18]Kyung-Sub Son, Kyongsu Lee
On-chip jitter tolerance measurement technique for CDR circuits. ISCAS 2015: 1602-1605 - 2014
- [j16]Taek-Joon Ahn, Sang-Soon Im, Yong-Sung Ahn, Jin-Ku Kang:
A low jitter clock and data recovery with a single edge sensing Bang-Bang PD. IEICE Electron. Express 11(7): 20140088 (2014) - [j15]Taek-Joon Ahn, Kyung-Sub Son, Yong-Sung Ahn, Jin-Ku Kang:
A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection. IEICE Electron. Express 11(17): 20140657 (2014) - [j14]Kyongsu Lee
A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS. IEICE Electron. Express 11(17): 20140671 (2014) - [j13]Yong-Sung Ahn, Taek-Joon Ahn, Kyongsu Lee
Avoiding noise frequency interference with binary phase pulse driving and CDS for capacitive TSP controller. IEICE Electron. Express 11(21): 20140837 (2014) - [j12]Hak Gu Kim, Jin-Ku Kang, Byung Cheol Song:
Automatic SfM-Based 2D-to-3D Conversion for Multi-Object Scenes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1159-1161 (2014) - [j11]Yong-Hwan Moon, In-Seok Kong, Young-Soo Ryu, Jin-Ku Kang:
A 2.2-mW 20-135-MHz False-Lock-Free DLL for Display Interface in 0.15-µm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 554-558 (2014) - [c17]Taek-Joon An, Kyung-Sub Son, Young-Jin Kim, In-Seok Kong, Jin-Ku Kang:
A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS. ISCAS 2014: 2329-2332 - 2013
- [j10]Benjamin P. Wilkerson, Joon-Hyup Seo, Jin-Cheol Seo, Jin-Ku Kang:
An ultra-low power BPSK demodulator with dual band filtering for implantable biomedical devices. IEICE Electron. Express 10(7): 20120896 (2013) - [c16]Hak Gu Kim, Jin-Ku Kang, Byung Cheol Song:
Three-dimensional perception improvement using sharpness adjustment and hardware implementation. ICME Workshops 2013: 1-4 - [c15]Benjamin P. Wilkerson, Jin-Ku Kang:
A low power BPSK demodulator for wireless implantable biomedical devices. ISCAS 2013: 626-629 - 2012
- [j9]Tae-Ho Kim, Jin-Cheol Seo, Yong-Sung Ahn, Jin-Ku Kang:
A 10Gb/s adaptive equalizer with ISI level measurement. IEICE Electron. Express 9(17): 1384-1390 (2012) - [j8]Tae Hwan Lee, Jin-Ku Kang, Byung Cheol Song:
Video denoising using overlapped motion compensation and advanced collaborative filtering. J. Electronic Imaging 21(2): 023004 (2012) - [c14]Benjamin P. Wilkerson, Jin-Ku Kang:
A non-coherent BPSK receiver with dual band filtering for implantable biomedical devices. ICECS 2012: 697-700 - [c13]Seung-Wuk Oh, Sang-Ho Kim, Jin-Ku Kang:
An audio clock regenerator with a wide dividing ratio for HDMI. ISCAS 2012: 2019-2022 - [c12]Jin-Cheol Seo, Tae-Ho Kim, Taek-Joon An, Kwan Yoon, Jin-Ku Kang:
A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern. ISOCC 2012: 419-422 - [c11]Seung-Wook Oh, Hyung-Min Park, Joon-Hyup Seo, Jae-Young Jang, Gi-Yeol Bae, Jin-Ku Kang:
A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS. ISOCC 2012: 423-426 - [c10]Jin-Cheol Seo, Sang-Soon Im, Kwan-Hee Yoon, Seung-Wook Oh, Taek-Joon An, Gi-Yeol Bae, Jin-Ku Kang:
A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. SoCC 2012: 57-60 - 2011
- [j7]Sungjae Lee, Jin-Ku Kang, Inhwan Lee:
Way-lookup buffer for low-power set-associative cache. IEICE Electron. Express 8(23): 1961-1966 (2011) - [j6]Tae-Ho Kim, Yong-Hwan Moon, Jin-Ku Kang:
A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement. IEICE Trans. Electron. 94-C(11): 1779-1786 (2011) - [c9]Tae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang:
A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement. ESSCIRC 2011: 351-354 - [c8]Benjamin P. Wilkerson, Tae-Ho Kim, Jin-Ku Kang:
Low-power non-coherent data and power recovery circuit for implantable biomedical devices. ISOCC 2011: 171-174 - 2010
- [j5]Tae-Ho Kim, Sang-Ho Kim, Jin-Ku Kang:
A DLL-based Clock Data Recovery with a modified input format. IEICE Electron. Express 7(8): 539-545 (2010) - [j4]Hyung-Min Park, Hyun-Bae Jin, Jin-Ku Kang:
SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators. IEICE Electron. Express 7(18): 1349-1353 (2010) - [c7]Sang-Ho Kim, Hyung-Min Park, Tae-Ho Kim, Jin-Ku Kang, Jin-Ho Kim
A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS. SoCC 2010: 84-87 - [c6]Jae-Wook Yoo, Tae-Ho Kim, Dong-Kyun Kim, Jin-Ku Kang:
A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2. SoCC 2010: 88-91
2000 – 2009
- 2009
- [c5]Seungwon Lee, Tae-Ho Kim, Jae-Wook Yoo, Jin-Ku Kang:
A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS. SoCC 2009: 179-182 - 2008
- [j3]Yong-Woo Kim, Beomseok Shin, Jin-Ku Kang:
High-speed 8B/10B encoder design using a simplified coding table. IEICE Electron. Express 5(16): 581-585 (2008) - [c4]Yong-Woo Kim
An 8B/10B encoder with a modified coding table. APCCAS 2008: 1522-1525 - 2005
- [c3]Hyung-Wook Jang, Sung-Sop Lee, Jin-Ku Kang:
A clock recovery circuit using half-rate 4×-oversampling PD. ISCAS (3) 2005: 2192-2195 - [c2]Sung-Sop Lee, Hyung-Wook Jang, Jin-Ku Kang:
3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling. SoCC 2005: 11-14 - 2002
- [j2]Chang-Hoon Lee, Seung-Ho Park, Jin-Ku Kang, Choon-Woo Kim:
A real time image processor for reproduction of gray levels in dark areas on plasma display panel (PDP). IEEE Trans. Consumer Electron. 48(4): 879-886 (2002) - 2001
- [c1]Jin-Ku Kang, Dong-Hee Kim:
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit. ISCAS (4) 2001: 266-269
1990 – 1999
- 1997
- [j1]Jin-Ku Kang, Wentai Liu, Ralph K. Cavin III:
A CMOS high-speed data recovery circuit using the matched delay sampling technique. IEEE J. Solid State Circuits 32(10): 1588-1596 (1997)
Coauthor Index
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last updated on 2024-10-04 20:01 CEST by the dblp team
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