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Kwang-Chun Choi
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2010 – 2019
- 2014
- [j5]Joung-Wook Moon, Kwang-Chun Choi, Woo-Young Choi:
A 0.4-V, 90 ∼ 350-MHz PLL With an Active Loop-Filter Charge Pump. IEEE Trans. Circuits Syst. II Express Briefs 61-II(5): 319-323 (2014) - 2013
- [j4]Kwang-Chun Choi, Sung-Geun Kim, Seung-Woo Lee, Bhum-Cheol Lee, Woo-Young Choi:
A 990-µW 1.6-GHz PLL Based on a Novel Supply-Regulated Active-Loop-Filter VCO. IEEE Trans. Circuits Syst. II Express Briefs 60-II(6): 311-315 (2013) - 2012
- [j3]Kwang-Chun Choi, Seung-Woo Lee, Bhum-Cheol Lee, Woo-Young Choi:
A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 143-147 (2012) - [c2]Jinsoo Rhim, Kwang-Chun Choi, Woo-Young Choi:
A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology. ISOCC 2012: 104-107 - 2010
- [j2]Kwang-Chun Choi, Minsu Ko, Duho Kim, Woo-Young Choi:
Demonstration of 60-GHz Link Using a 1.6-Gb/s Mixed-Mode BPSK Demodulator. IEICE Trans. Electron. 93-C(12): 1704-1707 (2010) - [c1]Duho Kim, Minsu Ko, Kwang-Chun Choi, Woo-Young Choi:
A 4.8-Gb/s mixed-mode CMOS QPSK demodulator for 60-GHz wireless personal area networks. APCCAS 2010: 60-63
2000 – 2009
- 2008
- [j1]Duho Kim, Kwang-Chun Choi, Young-Kwang Seo, Hyunchin Kim, Woo-Young Choi:
A 622-Mb/s Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector. IEEE J. Solid State Circuits 43(10): 2284-2292 (2008)
Coauthor Index
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