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Hyo-Sig Won
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2010 – 2019
- 2017
- [c5]Byung-Su Kim, Hyo-Sig Won, Tae Hee Han
, Joon-Sung Yang:
Non-linear library characterization method for FinFET logic cells by L1-minimization. ISCAS 2017: 1-4 - 2016
- [j4]Hanwool Jeong
Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1059-1063 (2016) - [c4]Byung-Su Kim, Hyo-Sig Won, Tae Hee Han, Joon-Sung Yang:
AFSEM: Advanced frequent subcircuit extraction method by graph mining approach for optimized cell library developments. ISCAS 2016: 662-665 - [c3]Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Jonghoon Jung, Giyong Yang
17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. ISSCC 2016: 306-307 - 2015
- [j3]Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang
A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. IEEE J. Solid State Circuits 50(1): 158-169 (2015) - [j2]Hanwool Jeong, Taewon Kim, Younghwi Yang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1062-1070 (2015) - [j1]Hanwool Jeong, Taewon Kim, Kyoman Kang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung:
Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1555-1563 (2015) - 2012
- [c2]Chungki Oh, Hyung-Ock Kim, Jun Seomun, Wook Kim, Jaehan Jeon, Kyung Tae Do, Hyo-Sig Won, Kee Sup Kim:
Thermal-aware body bias modulation for high performance mobile core. ISOCC 2012: 147-150
2000 – 2009
- 2003
- [c1]Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong:
An MTCMOS design methodology and its application to mobile computing. ISLPED 2003: 110-115
Coauthor Index
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