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ACM Great Lakes Symposium on VLSI 2021: Virtual Event, USA
- Yiran Chen, Victor V. Zhirnov, Avesta Sasan, Ioannis Savidis:
GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021. ACM 2021, ISBN 978-1-4503-8393-6
Session 1A: VLSI for Machine Learning and Artificial Intelligence I
- Mengdi Wang
, Bing Li, Ying Wang, Cheng Liu, Xiaohan Ma
MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design. 1-8 - Kyle Shiflett, Avinash Karanth, Ahmed Louri, Razvan C. Bunescu:
Bitwise Neural Network Acceleration Using Silicon Photonics. 9-14 - Yilong Zhao
Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication. 15-20 - Chengsi Gao, Bing Li, Ying Wang, Weiwei Chen, Lei Zhang:
Tenet: A Neural Network Model Extraction Attack in Multi-core Architecture. 21-26
Session 1B: Computer-Aided Design (CAD) I
- Muhammad Awais, Hassan Ghasemzadeh Mohammadi, Marco Platzner:
LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. 27-32 - Lucas Klemmer
EPEX: Processor Verification by Equivalent Program Execution. 33-38 - Nan Wu
IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning. 39-44 - Han Wang, Longfei Luo
SFP: Smart File-Aware Prefetching for Flash based Storage Systems. 45-50
Session 2A: Emerging Computing & Post-CMOS Technologies
- Rongliang Fu
Equivalence Checking for Superconducting RSFQ Logic Circuits. 51-56 - Zamshed I. Chowdhury, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jianping Wang, Ulya R. Karpuzcu:
CAMeleon: Reconfigurable B(T)CAM in Computational RAM. 57-63 - Zijing Niu, Honglan Jiang, Mohammad Saeed Ansari, Bruce F. Cockburn, Leibo Liu, Jie Han:
A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks. 65-70 - Tao Song, Xiaoming Chen, Yinhe Han:
Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in O(1) with RRAM-based In-Memory Accelerator. 71-76
Session 2B: Hardware Security I
- Satwik Patnaik:
On the Vulnerability of Hardware Masking in Practical Implementations. 77-82 - Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui:
The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing. 83-88 - Pranesh Santikellur, Rijoy Mukherjee, Rajat Subhra Chakraborty:
APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network. 89-94
Panel: Security Challenges in SoC Design
- Ahmad-Reza Sadeghi, Jeyavijayan Rajendran, Rahul Kande:
Organizing The World's Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned. 95-100
Session 3A: VLSI Design
- Bobby Bose, Ishan G. Thakkar:
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs. 101-107 - Partha Sarathi Paul, Maisha Sadia, Md Razuan Hossain, Barry J. Muldrey, Md Sakib Hasan
Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic Maps. 109-114 - Zheng Wang, Zhuo Wang, Jian Liao, Chao Chen, Yongkui Yang, Bo Dong, Weiguang Chen, Wenxuan Chen, Ming Lei, Weiyu Guo, Rui Chen, Yi Peng, Zhibin Yu:
CNN-DMA: A Predictable and Scalable Direct Memory Access Engine for Convolutional Neural Network with Sliding-window Filtering. 115-121 - S. Sivakumar, T. M. Abdul Khader, John Jose:
Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning. 123-128
Session 3B: Computer-Aided Design (CAD) II
- Rui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Liang Shi, Shouzhen Gu, Yan Hou:
Relaxed Placement: Minimizing Shift Operations for Racetrack Memory in Hybrid SPM. 129-134 - M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design. 135-140 - Wei Zhang, Yongxiao Zhou, Tsung-Yi Ho
Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table. 141-146 - Jürgen Maier
A Composable Glitch-Aware Delay Model. 147-154
Keynote II: Vivian Kammler
- Vivian Guzman Kammler:
Evolving Trust for High Consequence Microelectronics. 155
Session 4A: AAA in ML: Machine Learning Algorithm/Architecture/Accelerator Co-Design
- Yao Chen
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low Bitwidth Quantization, and Ultra-Low Latency Acceleration. 157-162 - Panjie Qi, Yuhong Song, Hongwu Peng
Accommodating Transformer onto FPGA: Coupling the Balanced Model Compression and FPGA-Implementation Optimization. 163-168 - Shaoyi Huang, Shiyang Chen
HMC-TRAN: A Tensor-core Inspired Hierarchical Model Compression for Transformer-based DNNs on GPU. 169-174 - Daniel Manu, Shaoyi Huang, Caiwen Ding, Lei Yang:
Co-Exploration of Graph Neural Network and Network-on-Chip Design Using AutoML. 175-180
Session 4B: Secure Machine Learning with CAD
- Sayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj P. D., Ioannis Savidis, Houman Homayoun, Avesta Sasan:
A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop. 181-187 - Micah Gorsline, James Smith, Cory E. Merkel:
On the Adversarial Robustness of Quantized Neural Networks. 189-194 - Neha Nagarkar, Khaled N. Khasawneh, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao:
Energy-Efficient and Adversarially Robust Machine Learning with Selective Dynamic Band Filtering. 195-200 - Siddharth Barve
Adversarial Attack Mitigation Approaches Using RRAM-Neuromorphic Architectures. 201-206
Session 5A: New Trends in Hardware Security: Provisioning for Testing, Attack Resilience, and Lightweight Cryptography
- Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj
The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities. 207-212 - Saran Phatharodom, Avesta Sasan, Ioannis Savidis:
SAT-attack Resilience Measure for Access Restricted Circuits. 213-220 - Shervin Roshanisefat, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits. 221-228 - Abubakr Abdulgadir, Sammy Lin, Farnoud Farahmand, Jens-Peter Kaps
Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security. 229-234
Session 5B: VLSI for Machine Learning and Artificial Intelligence II
- Cheng Chu, Fan Chen, Dawen Xu, Ying Wang:
RECOIN: A Low-Power Processing-in-ReRAM Architecture for Deformable Convolution. 235-240 - Bo Jiao, Haozhe Zhu
Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. 241-246 - Mohammadreza Baharani
DeepDive: An Integrative Algorithm/Architecture Co-Design for Deep Separable Convolutional Neural Networks. 247-252 - Fangxin Liu, Wenbo Zhao, Zongwu Wang, Tao Yang, Li Jiang:
IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration. 253-258
Session 6A: Poster Session I
- Mustafa Munir
qMC: A Formal Model Checking Verification Framework For Superconducting Logic. 259-264 - Shaahin Angizi, Arman Roohi, MohammadReza Taheri, Deliang Fan:
Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study. 265-270 - Mingdai Yang, Mohammad Reza Jokar, Junyi Qiu, Qiuwen Lou, Yuming Liu, Aditi Udupa, Frederic T. Chong
A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical Signals. 271-276 - Chen Dong, Lingqing Liu, Ximeng Liu, Huangda Liu, Sihuang Lian:
MEDASec: Logic Encryption Scheme for Micro-electrode-dot-array Biochips IP Protection. 277-282 - Joel Mandebi Mbongue, Sujan Kumar Saha, Christophe Bobda:
Domain Isolation in FPGA-Accelerated Cloud and Data Center Applications. 283-288 - Hui Chen, Zihao Zhang, Peng Chen, Shien Zhu
Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs. 289-294 - Abhinish Anand, Winnie Thomas, Suryakant Toraskar, Virendra Singh:
Predictive Warp Scheduling for Efficient Execution in GPGPU. 295-300
Session 6B: Testing, Reliability, Fault-Tolerance
- Aibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard, Xiaoqing Wen:
A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments. 301-306 - Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. 307-312 - Yu Ma, Linfeng Zheng, Pingqiang Zhou:
Tolerating Stuck-at Fault and Variation in Resistive Edge Inference Engine via Weight Mapping. 313-318
Keynote III: Len Orlando
- Pompei Len Orlando:
An Air Force Perspective on the Application of Machine Learning for Microelectronics Design and Security. 319
Session 7A: Poster Session II
- Pascal Pieper
Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level. 321-326 - Zhou Jin, Tian Feng
PALBBD: A Parallel ArcLength Method Using Bordered Block Diagonal Form for DC Analysis. 327-332 - Jinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu
ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. 333-338 - Siva Satyendra Sahoo, Akhil Raj Baranwal
MemOReL: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems. 339-346 - Chen Nie, Jie Lin, Huan Hu, Li Jiang, Xiaoyao Liang, Zhezhi He:
Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support. 347-352 - Shiwei Liu, Zihao Zhao, Yanhong Wang, Qiaosha Zou, Yiyun Zhang, Chuanjin Richard Shi:
Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing. 353-358
Session 7B: VLSI Circuits and Power Aware Design
- Prattay Chowdhury, Benjamin Carrión Schäfer:
Unlocking Approximations through Selective Source Code Transformations. 359-364 - Zhiyang Chen, Weiqing Ji, Yihao Peng
Machine Learning Based Acceleration Method for Ordered Escape Routing. 365-370 - Yashaswi Mannepalli, Viraj Bharadwaj Korede, Madhav Rao:
Novel Approximate Multiplier Designs for Edge Detection Application. 371-377
Session 8A: Towards Energy-efficient Machine Learning: Algorithm, Hardware and Computing Paradigm
- Shravya Channamadhavuni, Sven Thijssen, Sumit Kumar Jha
Accelerating AI Applications using Analog In-Memory Computing: Challenges and Opportunities. 379-384 - Hengyi Li, Zhichen Wang, Xuebin Yue
A Comprehensive Analysis of Low-Impact Computations in Deep Learning Workloads. 385-390 - Mingshuo Liu, Kevin Han, Shiyi Luo, Mingze Pan, Mousam Hossain, Bo Yuan, Ronald F. DeMara, Yu Bai:
An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance Dataset. 391-396 - Alejandro Hernández-Cano, Cheng Zhuo, Xunzhao Yin, Mohsen Imani:
Real-Time and Robust Hyperdimensional Classification. 397-402
Session 8B: Hardware Security II
- Yanan Guo
IVcache: Defending Cache Side Channel Attacks via Invisible Accesses. 403-408 - Geraldine Shirley Nicholas, Bhavin Thakar, Fareena Saqib:
Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V. 409-414 - Zhiming Zhang, Ivan Miketic, Emre Salman, Qiaoyan Yu:
Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking. 415-420
Keynote IV: Alex Jones
- Alex K. Jones
Tuning Memory Fault Tolerance on the Edge. 421-424
Session 9A: Microelectronic Systems Education
- Patrick Schaumont:
Socially-Distant Hands-On Labs for a Real-time Digital Signal Processing Course. 425-430 - Zhixiong Di, Yongming Tang, Jiahua Lu, Zhaoyang Lv:
ASIC Design Principle Course with Combination of Online-MOOC and Offline-Inexpensive FPGA Board. 431-436 - John A. Nestor:
Experiences with Remote Teaching an Embedded Systems Course. 437-442
Session 9B: Emerging Security Topics in Neural Networks
- Omid Aramoon, Gang Qu:
Provably Accurate Memory Fault Detection Method for Deep Neural Networks. 443-448 - Jiliang Zhang, Junjie Hou:
Unpaired Image-to-Image Translation Network for Semantic-based Face Adversarial Examples Generation. 449-454 - Mingfu Xue, Jian Wang, Weiqiang Liu:
DNN Intellectual Property Protection: Taxonomy, Attacks and Evaluations (Invited Paper). 455-460 - He Li, Yaru Pang, Jiliang Zhang:
Security Enhancements for Approximate Machine Learning. 461-466
Session 10A: Ferroelectric Technology: From Devices to Systems
- Shamiul Alam
Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offs. 467-472 - Shan Deng, Zijian Zhao, Santosh Kurinec, Kai Ni, Yi Xiao, Tongguang Yu, Vijaykrishnan Narayanan
Overview of Ferroelectric Memory Devices and Reliability Aware Design Optimization. 473-478 - Nuo Xiu, Yiming Chen, Guodong Yin
Capacitive Content-Addressable Memory: A Highly Reliable and Scalable Approach to Energy-Efficient Parallel Pattern Matching Applications. 479-484 - Mohammad Khairul Bashar, Jaykumar Vaidya, R. S. Surya Kanthi, Chonghan Lee, Feng Shi
Ferroelectric-based Accelerators for Computationally Hard Problems. 485-489
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