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Yunzhengmao Wang
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2020 – today
- 2024
- [j2]Yinglin Yang, Yunzhengmao Wang
, Tengyue Yi, Chixiao Chen, Qi Liu:
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration. Integr. 96: 102170 (2024) - [j1]Shiwei Liu
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 269-282 (2024) - 2023
- [c5]Hao Jiang, Jiapei Zheng, Yunzhengmao Wang
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. ISCAS 2023: 1-5 - [c4]Shiwei Liu, Peizhe Li, Jinshan Zhang, Yunzhengmao Wang
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. ISSCC 2023: 250-251 - 2022
- [c3]Chen Mu, Yunzhengmao Wang
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. AICAS 2022: 222-225 - [c2]Haozhe Zhu
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC 2022: 1-3 - 2021
- [c1]Jinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu
ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. ACM Great Lakes Symposium on VLSI 2021: 333-338
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last updated on 2024-10-07 21:18 CEST by the dblp team
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