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25th FPL 2015: London, United Kingdom
- 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015. IEEE 2015, ISBN 978-0-9934-2800-5
- Peter Y. K. Cheung, Wayne Luk, Cristina Silvano
:
Preface. 1-2 - Philip Heng Wai Leong
Significant papers from the first 25 years of the FPL conference. 1-3 - Pavel Burovskiy, Paul Grigoras, Spencer J. Sherwin
Efficient assembly for high order unstructured FEM meshes. 1-6 - Alric Althoff, Ryan Kastner
A scalable FPGA architecture for nonnegative least squares problems. 1-8 - Stylianos I. Venieris
Towards heterogeneous solvers for large-scale linear systems. 1-8 - Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones:
A software configurable coprocessor-based state-space controller. 1-6 - Hiroki Nakahara, Tsutomu Sasao:
A deep convolutional neural network based on nested residue number system. 1-6 - Skand Hurkat
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. 1-8 - Daniel Llamocca
A scalable pipelined architecture for biomimetic vision sensors. 1-6 - Carlos González, Daniel Mozos, Sebastián López
FPGA implementation to estimate the number of endmembers in hyperspectral images. 1-8 - Yun Rock Qu, Viktor K. Prasanna:
Power-efficient range-match-based packet classification on FPGA. 1-8 - Yoko Sogabe, Tsutomu Maruyama:
A variable length hash method for faster short read mapping on FPGA. 1-6 - Yaman Umuroglu, Donn Morrison, Magnus Jahre
Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform. 1-8 - João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. 1-8 - Ze-ke Wang, Bingsheng He
A study of data partitioning on OpenCL-based FPGAs. 1-8 - Nachiket Kapre, Jayakrishnan Selva Kumar, Parjanya Gupta, Sagar Shrishailappa Masuti
Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications. 1-8 - Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston:
Recursive pipelined genetic propagation for bilevel optimisation. 1-6 - Ren Chen, Viktor K. Prasanna:
Automatic generation of high throughput energy efficient streaming architectures for arbitrary fixed permutations. 1-8 - Oluseyi A. Ayorinde, He Qi, Yu Huang, Benton H. Calhoun:
Using island-style bi-directional intra-CLB routing in low-power FPGAs. 1-7 - Mohammad Hosseinabady
Energy optimization of FPGA-based stream-oriented computing with power gating. 1-6 - Ali Ahari, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs. 1-6 - João Carlos Resende, Ricardo Chaves
Compact dual block AES core on FPGA for CCM Protocol. 1-8 - Chaohui Du, Guoqiang Bai:
Towards efficient discrete Gaussian sampling for lattice-based cryptography. 1-6 - Marco Indaco, Fabio Lauri, Andrea Miele, Pascal Trotta:
An efficient many-core architecture for Elliptic Curve Cryptography security assessment. 1-6 - Zia Uddin Ahamed Khan, Mohammed Benaissa:
High speed ECC implementation on FPGA over GF(2m). 1-6 - Nicholas J. Fraser, Duncan J. M. Moss, JunKyu Lee
A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisation. 1-6 - Iman Ahmadpour, Behnam Khaleghi, Hossein Asadi
An efficient reconfigurable architecture by characterizing most frequent logic functions. 1-6 - Hao Liang
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. 1-8 - Jin Hee Kim, Jason Helge Anderson:
Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. 1-8 - Nachiket Kapre, Jan Gray:
Hoplite: Building austere overlay NoCs for FPGAs. 1-8 - Alessandro Cilardo:
Variable-latency signed addition on FPGAs. 1-6 - Marco Minutoli
Inter-procedural resource sharing in High Level Synthesis through function proxies. 1-8 - Zeping Xue, David B. Thomas:
SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems. 1-7 - Nuno Neves
Efficient data-stream management for shared-memory many-core systems. 1-8 - Siddharth Advani, Yasuki Tanabe, Kevin M. Irick, Jack Sampson, Vijaykrishnan Narayanan:
A scalable architecture for multi-class visual object detection. 1-8 - Rui Policarpo Duarte, Mário P. Véstias
Enhancing stochastic computations via process variation. 1-7 - Petr Pfeifer:
AmBRAMs - An analysis tool, method and framework for advanced measurements and reliability assessments on modern nanoscale FPGAs. 1 - Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano:
7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. 1 - Mohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz:
Design and simulation tools for Embedded NOCs on FPGAs. 1 - Noa Zilberman
NetFPGA - rapid prototyping of high bandwidth devices in open source. 1 - Zsolt István, David Sidler, Gustavo Alonso:
Building a distributed key-value store with FPGA-based microservers. 1 - Zoltan Lehoczky, Richárd Tóth, Krisztian Somogyi:
High-level FPGA logic synthesis from .NET programs for software developers. 1 - Hao Liang, Wei Zhang
Hierarchical library based power estimator for versatile FPGAs. 1 - Rui Fiel Cordeiro, Andre Prata, Arnaldo S. R. Oliveira
FPGA-based all-digital software defined radio system demonstration. 1 - Tze Hon Tan
rrBox: A remote dynamically reconfigurable network processing middlebox. 1-4 - Mudhar Bin Rabieah, Christos-Savvas Bouganis
FPGA based nonlinear Support Vector Machine training using an ensemble learning. 1-4 - Henry Block, Tsutomu Maruyama:
An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimization. 1-4 - Sebastian Friston
Ultra low latency dataflow renderer. 1-4 - Stefan Wonneberger, Peter Mühlfellner, Pedro Ceriotti, Thorsten Graf, Rolf Ernst:
Parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems. 1-4 - Sang Woo Jun
A transport-layer network for distributed FPGA platforms. 1-4 - Nikolaos Alachiotis:
Generating FPGA accelerators for chemical similarity assessment. 1-4 - Teng Xu, Hongxiang Gu, Miodrag Potkonjak:
Data protection using recursive inverse function. 1-4 - He Qi, Oluseyi A. Ayorinde, Yu Huang, Benton H. Calhoun:
Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs. 1-4 - Roel Oomen, Tuan D. A. Nguyen, Akash Kumar
An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs. 1-4 - Qi Chen, Qiang Liu:
Pipelined NoC router architecture design with buffer configuration exploration on FPGA. 1-4 - Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Accurate power analysis for near-Vt RRAM-based FPGA. 1-4 - Tahsin Turker Mutlugun, Sheng-De Wang:
OpenCL computing on FPGA using multiported shared memory. 1-4 - Xiaobin Liu, Tedy Thomas, Alan Boguslawski, Russell Tessier:
Adaptive MRAM-based CGRAs. 1-4 - Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa
Reduction calculator in an FPGA based switching Hub for high performance clusters. 1-4 - Khalid Javeed
Serial and parallel interleaved modular multipliers on FPGA platform. 1-4 - Giacomo Valente:
A framework for integrated monitoring of real-time embedded SoC. 1-2 - Jiasen Huang, Weina Lu, Junyan Ren:
Greedy approach based heuristics for partitioning SpMxV on FPGAs. 1-2 - Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo:
Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip. 1-2 - Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios
Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems. 1-2 - Timm Bostelmann, Sergei Sawitzki:
Towards a guided design flow for heterogeneous reconfigurable architectures. 1-2 - Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios
High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs. 1-2 - Andre Prata, Arnaldo S. R. Oliveira
FPGA-based all-digital Software Defined Radio receiver. 1-2 - Zakarya Guettatfi, Omar Kermia, Abdelhakim Khouas:
Over effective hard real-time hardware tasks scheduling and allocation. 1-2 - Rui Fiel Cordeiro, Arnaldo S. R. Oliveira
FPGA-based all-digital transmitters. 1-2 - Sen Ma, Zeyad Aklah, David Andrews
A run time interpretation approach for creating custom accelerators. 1-4 - Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura:
Data-triggered breakpoint for in-circuit debug without re-implementation. 1-4 - Nizar Dahir
Characterisation of feasibility regions in FPGAs under adaptive DVFS. 1-4 - Andrei-Dumitru Oancea, Christian Stüllein, Jano Gebelein, Udo Kebschull:
A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA. 1-4 - Jian Yan, Jifang Jin, Ying Wang, Xuegong Zhou, Philip H. W. Leong
UniStream: A unified stream architecture combining configuration and data processing. 1-4 - Nicolae Bogdan Grigore, Dirk Koch:
Placing partially reconfigurable stream processing applications on FPGAs. 1-4 - Stefano Di Carlo
A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs. 1-4 - Ioannis Chadjiminas, Christos Kyrkou
In-field vulnerability analysis of hardware-accelerated computer vision applications. 1-4 - Wolfgang Büter, Alberto García Ortiz
A rapid prototyping framework for nano-photonic accelerators. 1-4 - Libo Huang, Yongwen Wang, Qiang Dou, Chengyi Zhang, Caixia Sun, Chao Xu:
Fast FPGA system for microarchitecture optimization on synthesizable modern processor design. 1-4 - Kai-Uwe Irrgang, Thomas B. Preußer:
An LZ77-style bit-level compression for trace data compaction. 1-4 - Eddie Hung:
Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry. 1-4 - Oleg Petelin, Vaughn Betz:
Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks. 1-4 - Xiaotong Li, Benjamin Carrión Schäfer:
Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs. 1-4 - Berg Severens, Elias Vansteenkiste, Karel Heyse, Dirk Stroobandt:
Estimating circuit delays in FPGAs after technology mapping. 1-4 - Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews
Automatic support for multi-module parallelism from computational patterns. 1-8 - Chin Hau Hoo, Akash Kumar
ParaLaR: A parallel FPGA router based on Lagrangian relaxation. 1-6 - Yuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu
Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs. 1-8 - Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne:
A technology mapper for depth-constrained FPGA logic cells. 1-8 - Mark Wijtvliet, Shakith Fernando, Henk Corporaal:
SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species. 1-6 - Mohammad Hosseinabady
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. 1-6 - Gabriel Weisz, James C. Hoe:
CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing. 1-8 - Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer:
Scavenger: Automating the construction of application-optimized memory hierarchies. 1-8 - Julian Oppermann, Andreas Koch, Ting Yu, Oliver Sinnen
Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators. 1-7 - Stephan Werner, Leonard Masing, Fabian Lesniak, Jürgen Becker
Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms. 1-8 - Thiem Van Chu, Shimpei Sato, Kenji Kise:
Ultra-fast NoC emulation on a single FPGA. 1-8 - Meena Belwal
Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions. 1-8 - Zdravko Panjkov, Andreas Wasserbauer, Timm Ostermann, Richard Hagelauer:
Hybrid FPGA debug approach. 1-8 - Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica:
PushPush: Seamless integration of hardware and software objects via function calls over AXI. 1-8
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