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Shimpei Sato
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2020 – today
- 2024
- [c39]Yoshihiro Maeda, Taishi Yazawa, Shimpei Sato, Wataru Hara:
On Relation Between Leakage-Free Condition and Differential Filtering Order in ETFE-Based Frequency Responce Function Estimation*. AIM 2024: 824-829 - [c38]Daigo Yamaguchi, Shimpei Sato, Yoshihiro Maeda:
Direct Data-Driven Control-Based Additive Feedforward Compensation for Fast and Precise Positioning Control. AIM 2024: 1203-1210 - 2023
- [c37]Takuma Hiraoka, Shimpei Sato, Naoki Hiraoka, Annan Tang, Kunio Kojima, Kei Okada, Masayuki Inaba, Koji Kawasaki:
Whole-Body Torque Control Without Joint Position Control Using Vibration-Suppressed Friction Compensation for Bipedal Locomotion of Gear-Driven Torque Sensorless Humanoid. IROS 2023: 8544-8550 - [c36]Shimpei Sato, Kunio Kojima, Naoki Hiraoka, Kei Okada, Masayuki Inaba:
Humanoid Walking System with CNN-Based Uneven Terrain Recognition and Landing Control with Swing-Leg Velocity Constraints. IROS 2023: 10382-10389 - 2022
- [c35]Yohei Kakiuchi, Yuta Kojio, Noriaki Imaoka, Daiki Kusuyama, Shimpei Sato, Yutaro Matsuura, Takeshi Ando, Masayuki Inaba:
Trajectory Generation and Compensation for External Forces with a Leg-wheeled Robot Designed for Human Passengers. Humanoids 2022: 32-38 - [c34]Shimpei Sato, Yuta Kojio, Yohei Kakiuchi, Kunio Kojima, Kei Okada, Masayuki Inaba:
Robust Humanoid Walking System Considering Recognized Terrain and Robots' Balance. IROS 2022: 8298-8305 - 2021
- [j14]Naoto Soga, Shimpei Sato, Hiroki Nakahara
:
Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder. IEICE Trans. Inf. Syst. 104-D(8): 1121-1129 (2021) - [j13]Akira Jinguji
Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. IEICE Trans. Inf. Syst. 104-D(12): 2040-2047 (2021) - [c33]Shimpei Sato, Yuta Kojio, Kunio Kojima, Fumihito Sugai, Yohei Kakiuchi, Kei Okada, Masayuki Inaba:
Drop Prevention Control for Humanoid Robots Carrying Stacked Boxes. IROS 2021: 4118-4125 - 2020
- [j12]Shimpei Sato, Kano Akagi, Atsushi Takahashi
A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(9): 1037-1044 (2020) - [j11]Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. 103-D(12): 2463-2470 (2020) - [c32]Akira Jinguji, Shimpei Sato, Hiroki Nakahara:
Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. FCCM 2020: 229 - [c31]Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara:
Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops 2020: 143-146 - [c30]Yuta Suzuki, Naoto Soga, Shimpei Sato, Hiroki Nakahara
A Table Look-Up Based Ternary Neural Network Processor. ISMVL 2020: 188-193
2010 – 2019
- 2019
- [j10]Hiroki Nakahara
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. 102-D(5): 1003-1011 (2019) - [j9]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. 102-D(5): 1020-1028 (2019) - [j8]Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1760-1769 (2019) - [c29]Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato:
An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA 2019: 186 - [c28]Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato:
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL 2019: 180-186 - [c27]Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution. ISCAS 2019: 1-5 - [c26]Atsuki Munakata, Hiroki Nakahara
Noise Convolutional Neural Networks and FPGA Implementation. ISMVL 2019: 85-90 - [c25]Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC 2019: 93-100 - [c24]Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara:
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig 2019: 1-5 - 2018
- [j7]Shimpei Sato, Ryohei Kobayashi
ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment. IEICE Trans. Inf. Syst. 101-D(2): 344-353 (2018) - [j6]Akira Jinguji
An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design. IEICE Trans. Inf. Syst. 101-D(2): 354-362 (2018) - [j5]Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA. IEICE Trans. Inf. Syst. 101-D(2): 376-386 (2018) - [j4]Kota Ando
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - [c23]Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato:
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. FPGA 2018: 31-40 - [c22]Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato:
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL 2018: 457-458 - [c21]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL 2018: 461-462 - [c20]Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato:
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT 2018: 298-301 - [c19]Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara:
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. FPT 2018: 310-313 - [c18]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART 2018: 10:1-10:6 - [c17]Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara:
A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). HEART 2018: 20:1-20:4 - [c16]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. ISMVL 2018: 174-179 - [c15]Atsushi Takahashi
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. ISVLSI 2018: 494-497 - 2017
- [j3]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. ACM Trans. Reconfigurable Technol. Syst. 10(4): 27:1-27:27 (2017) - [c14]Hiroki Nakahara, Tomoya Fujii, Shimpei Sato:
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. FPL 2017: 1-4 - [c13]Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato:
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. FPT 2017: 168-175 - [c12]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
All binarized convolutional neural network and its implementation on an FPGA. FPT 2017: 291-294 - [c11]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS 2017: 116-119 - 2015
- [c10]Shimpei Sato, Kenji Kise:
ArchHDL: A Novel Hardware RTL Design Environment in C++. ARC 2015: 53-64 - [c9]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. FCCM 2015: 60-63 - [c8]Thiem Van Chu, Shimpei Sato, Kenji Kise:
Ultra-fast NoC emulation on a single FPGA. FPL 2015: 1-8 - [c7]Tomohiro Misono, Ryohei Kobayashi
Effective Parallel Simulation of ArchHDL under Manycore Environment. CANDAR 2015: 140-146 - [c6]Yukinori Sato
Exana: an execution-driven application analysis tool for assisting productive performance tuning. SEPS@SPLASH 2015: 1-10 - [c5]Shimpei Sato, Yukinori Sato
Investigating potential performance benefits of memory layout optimization based on roofline model. SEPS@SPLASH 2015: 50-56 - 2014
- [c4]Thiem Van Chu, Shimpei Sato, Kenji Kise:
KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. MCSoC 2014: 215-222 - 2013
- [j2]Yuichiro Tanaka, Shimpei Sato, Kenji Kise:
The Ultrasmall soft processor. SIGARCH Comput. Archit. News 41(5): 95-100 (2013) - 2010
- [c3]Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise:
Smart Core System for Dependable Many-Core Processor with Multifunction Routers. ICNC 2010: 133-139 - [c2]Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise:
Pattern-Based Systematic Task Mapping for Many-Core Processors. ICNC 2010: 173-178
2000 – 2009
- 2009
- [j1]Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise:
SimCell: A Processor Simulator for Multi-Core Architecture Research. Inf. Media Technol. 4(2): 270-281 (2009) - [c1]Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise:
A Study of an Infrastructure for Research and Development of Many-Core Processors. PDCAT 2009: 414-419
Coauthor Index
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