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Tuan D. A. Nguyen
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2020 – today
- 2021
- [j3]Salim Ullah
, Tuan Duy Anh Nguyen, Akash Kumar
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators. IEEE Embed. Syst. Lett. 13(2): 41-44 (2021) - [j2]Behnaz Ranjbar
Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2009-2023 (2021) - 2020
- [c13]Tuan D. A. Nguyen, Akash Kumar
Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment. FPGA 2020: 29-39 - [i1]Behnaz Ranjbar, Tuan D. A. Nguyen, Alireza Ejlali, Akash Kumar:
Power-Aware Run-Time Scheduler for Mixed-Criticality Systems on Multi-Core Platform. CoRR abs/2011.03262 (2020)
2010 – 2019
- 2019
- [j1]Siva Satyendra Sahoo
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems. Integr. 67: 95-107 (2019) - [c12]Behnaz Ranjbar
Online Peak Power and Maximum Temperature Management in Multi-core Mixed-Criticality Embedded Systems. DSD 2019: 546-553 - [c11]Nusrat Jahan Lisa
High-Throughput BitPacking Compression. DSD 2019: 643-646 - 2018
- [c10]Siva Satyendra Sahoo
Lifetime-aware design methodology for dynamic partially reconfigurable systems. ASP-DAC 2018: 393-398 - [c9]Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Wolfgang Lehner
FPGA vs. SIMD: Comparison for Main Memory-Based Fast Column Scan. DATA (Revised Selected Papers) 2018: 116-140 - [c8]Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Tuan D. A. Nguyen, Akash Kumar
Column Scan Optimization by Increasing Intra-Instruction Parallelism. DATA 2018: 344-353 - [c7]Siva Satyendra Sahoo
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning. FPT 2018: 230-233 - [c6]Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Wolfgang Lehner, Tuan D. A. Nguyen, Akash Kumar:
Column Scan Acceleration in Hybrid CPU-FPGA Systems. ADMS@VLDB 2018: 22-33 - 2016
- [c5]Tuan D. A. Nguyen, Akash Kumar:
PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems. FPGA 2016: 149-158 - [c4]Tuan D. A. Nguyen, Akash Kumar
XNoC: A non-intrusive TDM circuit-switched Network-on-Chip. FPL 2016: 1-11 - 2015
- [c3]Roel Oomen, Tuan D. A. Nguyen, Akash Kumar
An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs. FPL 2015: 1-4 - 2014
- [c2]Tuan D. A. Nguyen, Akash Kumar
PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems. FPL 2014: 1-6 - 2011
- [c1]Trung Hieu Bui, Tuan Duy Anh Nguyen, Ngoc Thinh Tran:
BBFEX: a bloom-bloomier filter extension for long patterns in FPGA-based pattern matching system (abstract only). FPGA 2011: 285
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