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"Variable-latency signed addition on FPGAs."

Alessandro Cilardo (2015)

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DOI: 10.1109/FPL.2015.7293957

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - https://dblp.org/rec/conf/fpl/Cilardo15
Alessandro Cilardo:
Variable-latency signed addition on FPGAs. FPL 2015: 1-6

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