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David B. Thomas
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- affiliation: Imperial College London, UK
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2020 – today
- 2024
- [j25]Jordan Morris
, Ashur Rafiev
An Event-Driven Approach to Genotype Imputation on a Custom RISC-V Cluster. IEEE ACM Trans. Comput. Biol. Bioinform. 21(1): 26-35 (2024) - 2023
- [j24]Mahyar Shahsavari
Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems. Array 20: 100323 (2023) - [j23]Mark Vousden
Event-based high throughput computing: A series of case studies on a massively parallel softcore machine. IET Comput. Digit. Tech. 17(1): 29-42 (2023) - [j22]Andrew D. Brown
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. 10(2): 7:1-7:32 (2023) - [i6]Jordan Morris, Ashur Rafiev, Graeme M. Bragg, Mark Vousden, David B. Thomas, Alex Yakovlev, Andrew Brown:
An Event-Driven Approach To Genotype Imputation On A Custom RISC-V FPGA Cluster. CoRR abs/2301.10005 (2023) - 2022
- [j21]Ashur Rafiev
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Comput. Digit. Tech. 16(2-3): 71-88 (2022) - [j20]Ashur Rafiev
Practical Distributed Implementation of Very Large Scale Petri Net Simulations. Trans. Petri Nets Other Model. Concurr. 16: 112-139 (2022) - [c84]Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas
Non-deterministic event brokered computing. HEART 2022: 84-86 - 2021
- [c83]Mahyar Shahsavari
Neuromorphic Design Using Reward-based STDP Learning on Event-Based Reconfigurable Cluster Architecture. ICONS 2021: 5:1-5:8 - [c82]Matthew Naylor, Simon W. Moore, David B. Thomas
General hardware multicasting for fine-grained message-passing architectures. PDP 2021: 126-133 - 2020
- [c81]Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas
Termination detection for fine-grained message-passing architectures. ASAP 2020: 17-24 - [c80]Tim Todman, David B. Thomas
Exploring performance enhancement of event-driven processor networks. FPT 2020: 300 - [c79]Alexander Rast, Mahyar Shahsavari
A Hardware/Application Overlay Model for Large-Scale Neuromorphic Simulation. IJCNN 2020: 1-9
2010 – 2019
- 2019
- [c78]David B. Thomas
Compile-Time Generation of Custom-Precision Floating-Point IP using HLS Tools. ARITH 2019: 192-193 - [c77]David B. Thomas
Templatised Soft Floating-Point for High-Level Synthesis. FCCM 2019: 227-235 - [c76]Florian Faissole, George A. Constantinides, David B. Thomas:
Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. FCCM 2019: 315 - [c75]Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. FPL 2019: 81-87 - [c74]Matthew Naylor, Simon W. Moore, David B. Thomas:
Tinsel: A Manythread Overlay for FPGA Clusters. FPL 2019: 375-383 - [c73]Andrew D. Brown, Mark Vousden, Alex Rast, Graeme M. Bragg, David B. Thomas, Jonny Beaumont, Matthew Naylor, Andrey Mokhov:
POETS: Distributed Event-Based Computing - Scaling Behaviour. PARCO 2019: 487-496 - 2018
- [j19]Aryan Tavakkoli
A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 341-354 (2018) - [c72]Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. ARC 2018: 16-28 - [c71]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC 2018: 29-42 - [c70]Shane T. Fleming, David B. Thomas:
Injecting FPGA Configuration Faults in Parallel. FPT 2018: 198-205 - [c69]Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung:
Accelerating Top-k ListNet Training for Ranking Using FPGA. FPT 2018: 242-245 - [i5]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR abs/1807.10577 (2018) - 2017
- [j18]Gordon Inggs
A Domain Specific Approach to High Performance Heterogeneous Computing. IEEE Trans. Parallel Distributed Syst. 28(1): 2-15 (2017) - [c68]Shane T. Fleming, David B. Thomas:
Using Runahead Execution to Hide Memory Latency in High Level Synthesis. FCCM 2017: 109-116 - [c67]Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas
Programming Model to Develop Supercomputer Combinatorial Solvers. ICPP Workshops 2017: 171-179 - [c66]Andrew D. Brown, David B. Thomas, Jeff Reeve, Ghaith Tarawneh, Alessandro de Gennaro, Andrey Mokhov, Matthew Naylor, Tom Kazmierski:
Distributed Event-Based Computing. PARCO 2017: 583-592 - 2016
- [j17]Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung:
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Comput. Archit. News 44(4): 68-73 (2016) - [c65]David B. Thomas
Synthesisable recursion for C++ HLS tools. ASAP 2016: 91-98 - [c64]Shane T. Fleming, David B. Thomas
StitchUp: automatic control flow protection for high level synthesis circuits. DAC 2016: 138:1-138:6 - [c63]Jiang Su, David B. Thomas
Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. FCCM 2016: 48-51 - [c62]Zeping Xue, David B. Thomas
SynADT: Dynamic Data Structures in High Level Synthesis. FCCM 2016: 64-71 - [c61]Peter Ogden, David B. Thomas, Peter R. Pietzuch:
AT-GIS: Highly Parallel Spatial Query Processing with Associative Transducers. SIGMOD Conference 2016: 1041-1054 - 2015
- [j16]Liucheng Guo, Andreea-Ingrid Funie, Zhongliu Xie, David B. Thomas, Wayne Luk:
A general-purpose framework for FPGA-accelerated genetic algorithms. Int. J. Bio Inspired Comput. 7(6): 361-375 (2015) - [j15]Takaaki Miyajima, David B. Thomas, Hideharu Amano:
Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms. IPSJ Trans. Syst. LSI Des. Methodol. 8: 105-115 (2015) - [j14]Takaaki Miyajima, David B. Thomas, Hideharu Amano:
A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms. J. Inf. Process. 23(2): 153-162 (2015) - [j13]Liucheng Guo, Andreea-Ingrid Funie, David B. Thomas, Haohuan Fu, Wayne Luk:
Parallel Genetic Algorithms on Multiple FPGAs. SIGARCH Comput. Archit. News 43(4): 86-93 (2015) - [j12]David B. Thomas:
The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator. ACM Trans. Reconfigurable Technol. Syst. 8(4): 23:1-23:22 (2015) - [c60]David B. Thomas:
A General-Purpose Method for Faithfully Rounded Floating-Point Function Approximation in FPGAs. ARITH 2015: 42-49 - [c59]David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica:
Transparent linking of compiled software and synthesized hardware. DATE 2015: 1084-1089 - [c58]Liucheng Guo, Ce Guo, David B. Thomas, Wayne Luk:
Pipelined Genetic Propagation. FCCM 2015: 103-110 - [c57]Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica:
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. FPGA 2015: 214-217 - [c56]Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica:
PushPush: Seamless integration of hardware and software objects via function calls over AXI. FPL 2015: 1-8 - [c55]Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston:
Recursive pipelined genetic propagation for bilevel optimisation. FPL 2015: 1-6 - [c54]Zeping Xue, David B. Thomas:
SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems. FPL 2015: 1-7 - [i4]Gordon Inggs, David B. Thomas, Wayne Luk:
An Efficient, Automatic Approach to High Performance Heterogeneous Computing. CoRR abs/1505.04417 (2015) - [i3]Gordon Inggs
Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service. CoRR abs/1506.06684 (2015) - 2014
- [c53]Liucheng Guo, David B. Thomas, Wayne Luk:
Automated Framework for General-Purpose Genetic Algorithms in FPGAs. EvoApplications 2014: 714-725 - [c52]David B. Thomas:
FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy. FCCM 2014: 149-156 - [c51]Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides:
Compiling Higher Order Functional Programs to Composable Digital Hardware. FCCM 2014: 234 - [c50]Shane T. Fleming, David B. Thomas:
Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs. FPL 2014: 1-6 - [c49]Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides:
Area implications of memory partitioning for high-level synthesis on FPGAs. FPL 2014: 1-4 - [c48]Liucheng Guo, David B. Thomas, Ce Guo, Wayne Luk:
Automated framework for FPGA-based parallel genetic algorithms. FPL 2014: 1-7 - [c47]Gordon Inggs
Is high level synthesis ready for business? A computational finance case study. FPT 2014: 12-19 - [c46]Aryan Tavakkoli
Low-latency option pricing using systolic binomial trees. FPT 2014: 44-51 - [i2]Gordon Inggs
A Domain Specific Approach to Heterogeneous Computing: From Availability to Accessibility. CoRR abs/1408.4965 (2014) - [i1]Takaaki Miyajima, David B. Thomas, Hideharu Amano:
An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms. CoRR abs/1408.4969 (2014) - 2013
- [j11]Peter Ogden, David B. Thomas, Peter R. Pietzuch:
Scalable XML Query Processing using Parallel Pushdown Transducers. Proc. VLDB Endow. 6(14): 1738-1749 (2013) - [j10]Liucheng Guo, David B. Thomas, Wayne Luk:
Customisable architectures for the set covering problem. SIGARCH Comput. Archit. News 41(5): 101-106 (2013) - [j9]David B. Thomas, Wayne Luk:
The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 761-770 (2013) - [j8]David B. Thomas, Wayne Luk:
Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2193-2205 (2013) - [c45]Shane T. Fleming, David B. Thomas:
Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields. ARC 2013: 103-114 - [c44]David B. Thomas:
Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform. FCCM 2013: 161-168 - [c43]Shane T. Fleming, David B. Thomas:
FPGA based control for real time systems. FPL 2013: 1-2 - [c42]David B. Thomas, Hideharu Amano:
A fully pipelined FPGA architecture for stochastic simulation of chemical systems. FPL 2013: 1-7 - [c41]Gordon Inggs
A Heterogeneous Computing Framework for Computational Finance. ICPP 2013: 688-697 - 2012
- [j7]Anson H. T. Tse, David B. Thomas, Wayne Luk:
Design Exploration of Quadrature Methods in Option Pricing. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 818-826 (2012) - [c40]Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston:
Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations. ARC 2012: 187-201 - [c39]Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk:
Optimising Performance of Quadrature Methods with Reduced Precision. ARC 2012: 251-263 - [c38]Brahim Betkaoui, Yu Wang
A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration. ASAP 2012: 8-15 - [c37]Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong
A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. FPGA 2012: 57-66 - [c36]Brahim Betkaoui, Yu Wang
Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. FPL 2012: 99-104 - [c35]Qiwei Jin, Tobias Becker
Optimising explicit finite difference option pricing for dynamic constant reconfiguration. FPL 2012: 165-172 - [c34]Gordon Inggs
Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA. FPL 2012: 695-698 - [c33]Takaaki Miyajima, David B. Thomas, Hideharu Amano:
A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU. ICNC 2012: 175-181 - 2011
- [b1]David B. Thomas:
Management and programming of reconfigurable hardware resources. Imperial College London, UK, 2011 - [c32]Qiwei Jin, Wayne Luk, David B. Thomas:
On Comparing Financial Option Price Solvers on FPGA. FCCM 2011: 89-92 - [c31]Qiwei Jin, Wayne Luk, David B. Thomas:
Unifying Finite Difference Option-Pricing for Hardware Acceleration. FPL 2011: 6-9 - [c30]Brahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj
A framework for FPGA acceleration of large graph problems: Graphlet counting case study. FPT 2011: 1-8 - 2010
- [j6]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk:
Efficient reconfigurable design for pricing asian options. SIGARCH Comput. Archit. News 38(4): 14-20 (2010) - [c29]David B. Thomas, Wayne Luk:
An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers. ASAP 2010: 208-215 - [c28]David B. Thomas, Wayne Luk:
FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers. FPL 2010: 77-82 - [c27]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk:
Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. FPL 2010: 364-367 - [c26]Brahim Betkaoui, David B. Thomas, Wayne Luk:
Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. FPT 2010: 94-101 - [c25]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk:
Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. FPT 2010: 233-240
2000 – 2009
- 2009
- [j5]Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope:
Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models. ACM Trans. Reconfigurable Technol. Syst. 2(4): 21:1-21:17 (2009) - [c24]Anson H. T. Tse, David B. Thomas, Wayne Luk:
Accelerating Quadrature Methods for Option Valuation. FCCM 2009: 29-36 - [c23]David B. Thomas, Wayne Luk:
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. FCCM 2009: 45-52 - [c22]David B. Thomas, Lee W. Howes, Wayne Luk:
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. FPGA 2009: 63-72 - [c21]Qiwei Jin, David B. Thomas, Wayne Luk:
Exploring reconfigurable architectures for explicit finite difference option pricing models. FPL 2009: 73-78 - [c20]Gareth W. Morris, David B. Thomas, Wayne Luk:
FPGA Accelerated Low-Latency Market Data Feed Processing. Hot Interconnects 2009: 83-89 - 2008
- [j4]David B. Thomas, Wayne Luk:
Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware. ACM Trans. Reconfigurable Technol. Syst. 1(2): 12:1-12:29 (2008) - [c19]Pedro Echeverría, David B. Thomas, Marisa López-Vallejo
An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC 2008: 219-230 - [c18]Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope:
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. ARC 2008: 243-253 - [c17]David B. Thomas, Wayne Luk:
Resource efficient generators for the floating-point uniform and exponential distributions. ASAP 2008: 102-107 - [c16]David B. Thomas, Wayne Luk:
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. FCCM 2008: 229-238 - [c15]David B. Thomas, Wayne Luk:
FPGA-optimised high-quality uniform random number generators. FPGA 2008: 235-244 - [c14]David B. Thomas, Wayne Luk:
Sampling from the exponential distribution using independent Bernoulli variates. FPL 2008: 239-244 - [c13]David B. Thomas, Wayne Luk:
Estimation of sample mean and variance for Monte-Carlo simulations. FPT 2008: 89-96 - 2007
- [j3]David B. Thomas, Wayne Luk, Philip Heng Wai Leong
Gaussian random number generators. ACM Comput. Surv. 39(4): 11 (2007) - [j2]David B. Thomas, Wayne Luk:
Non-uniform random number generation through piecewise linear approximations. IET Comput. Digit. Tech. 1(4): 312-321 (2007) - [j1]David B. Thomas, Wayne Luk:
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. J. VLSI Signal Process. 47(1): 77-92 (2007) - [c12]David B. Thomas, Wayne Luk, Michael Stumpf:
Reconfigurable Hardware Acceleration of Canonical Graph Labelling. ARC 2007: 302-313 - [c11]David B. Thomas, Jacob A. Bower, Wayne Luk:
Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. ASAP 2007: 168-173 - [c10]David B. Thomas, Wayne Luk:
Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. FCCM 2007: 3-12 - [c9]David B. Thomas, Wayne Luk:
A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations. FPT 2007: 97-104 - 2006
- [c8]David B. Thomas, Wayne Luk:
Efficient Hardware Generation of Random Variates with Arbitrary Distributions. FCCM 2006: 57-66 - [c7]David B. Thomas, Wayne Luk:
Non-Uniform Random Number Generation Through Piecewise Linear Approximations. FPL 2006: 1-6 - [c6]David B. Thomas, Jacob A. Bower, Wayne Luk:
Hardware architectures for Monte-Carlo based financial simulations. FPT 2006: 377-380 - [c5]Jacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer:
A Reconfigurable Simulation Framework for Financial Computation. ReConFig 2006: 30-38 - 2005
- [c4]David B. Thomas, Wayne Luk:
High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences. FPT 2005: 61-68 - [c3]David B. Thomas, Wayne Luk:
High quality uniform random number generation for massively parallel simulations in FPGA. ReConFig 2005 - 2004
- [c2]David B. Thomas, Wayne Luk:
Implementing Graphics Shaders Using FPGAs. FPL 2004: 1173 - [c1]Henry Styles, David B. Thomas, Wayne Luk:
Pipelining designs with loop-carried dependencies. FPT 2004: 255-262
Coauthor Index
[j24] [j23] [c84] [c83] [c80] [j18] [j16] [j13] [c58] [c55] [i4] [i3] [c53] [c48] [c47] [i2] [j10] [j9] [j8] [c41] [j7] [c40] [c39] [c38] [c37] [c36] [c35] [c32] [c31] [c30] [j6] [c29] [c28] [c27] [c26] [c25] [j5] [c24] [c23] [c22] [c21] [c20] [j4] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [j3] [j2] [j1] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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