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Rui Policarpo Duarte
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2020 – today
- 2023
- [j12]Maria Inês Frutuoso, Horácio C. Neto
, Mário P. Véstias
Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. Algorithms 16(3): 141 (2023) - [j11]Mário P. Véstias
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. 16(1): 13:1-13:36 (2023) - 2022
- [j10]Helena Cruz
A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. 14(5): 1258 (2022) - [j9]David Mota, Helena Cruz
Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 15: 3600-3611 (2022) - 2021
- [j8]Daniel Pestana, Pedro R. Miranda
A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access 9: 75864-75877 (2021) - [j7]Pedro R. Miranda
Configurable Hardware Core for IoT Object Detection. Future Internet 13(11): 280 (2021) - 2020
- [j6]Mário P. Véstias
A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access 8: 107229-107243 (2020) - [j5]Mário P. Véstias
Moving Deep Learning to the Edge. Algorithms 13(5): 125 (2020) - [j4]Mário P. Véstias
A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems 77: 103136 (2020) - [c20]Rui Policarpo Duarte
Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm. ARC 2020: 392-401
2010 – 2019
- 2019
- [j3]João Vieira
kNN-STUFF: kNN STreaming Unit for Fpgas. IEEE Access 7: 170864-170877 (2019) - [j2]Helena Cruz
Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection. J. Aerosp. Inf. Syst. 16(11): 512-520 (2019) - [c19]Helena Cruz
Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging. ARC 2019: 3-16 - [c18]Mário P. Véstias
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL 2019: 350-353 - [c17]Luís Fiolhais, Fernando M. Gonçalves
Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. ISCAS 2019: 1-5 - 2018
- [c16]Rui Policarpo Duarte, Horácio C. Neto
Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems. DSC 2018: 1-8 - [c15]Mário P. Véstias
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL 2018: 399-402 - [c14]Rui Policarpo Duarte, Álvaro Simões, Rui Henriques
FPGA-based OpenCL Accelerator for Discovering Temporal Patterns in Gene Expression Data Using Biclustering. PBio@EuroMPI 2018: 53-62 - 2017
- [c13]Mário P. Véstias
Parallel dot-products for deep learning on FPGA. FPL 2017: 1-4 - [i3]Daniel Porto, João Loff, Rui Policarpo Duarte
Making data center computations fast, but not so furious. CoRR abs/1704.05112 (2017) - [i2]Rui Policarpo Duarte:
Transport Protocols for Large Bandwidth-Delay Product Networks - TCP Extensions and Alternative Transport Protocols. CoRR abs/1705.08929 (2017) - 2016
- [c12]Rui Policarpo Duarte, Horácio C. Neto
XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. ICRC 2016: 1-7 - [c11]Rui Policarpo Duarte, Christos-Savvas Bouganis
Variation-Aware Optimisation for Reconfigurable Cyber-Physical Systems. DoCEIS 2016: 237-252 - [c10]Michail S. Vavouras, Rui Policarpo Duarte, Antonino Armato, Christos-Savvas Bouganis
A hybrid ASIC/FPGA fault-tolerant artificial pancreas. SAMOS 2016: 261-267 - 2015
- [j1]Rui Policarpo Duarte, Christos-Savvas Bouganis
ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation. ACM Trans. Reconfigurable Technol. Syst. 9(1): 7:1-7:17 (2015) - [c9]Rui Policarpo Duarte, Mário P. Véstias
Enhancing stochastic computations via process variation. FPL 2015: 1-7 - [c8]André Lourenço
CardioWheel: ECG Biometrics on the Steering Wheel. ECML/PKDD (3) 2015: 267-270 - [i1]Mário P. Véstias, Rui Policarpo Duarte, Horácio C. Neto:
Designing Hardware/Software Systems for Embedded High-Performance Computing. CoRR abs/1508.06832 (2015) - 2014
- [c7]Rui Policarpo Duarte, Christos-Savvas Bouganis
A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation. ARC 2014: 49-60 - [c6]Rui Policarpo Duarte, Christos-Savvas Bouganis:
Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only). FPGA 2014: 245 - [c5]Rui Policarpo Duarte, Christos-Savvas Bouganis
Over-clocking of Linear Projection Designs through Device Specific Optimisations. IPDPS Workshops 2014: 189-198 - [c4]Rui Policarpo Duarte, Christos-Savvas Bouganis
Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs. ReConFig 2014: 1-7 - 2012
- [c3]Rui Policarpo Duarte, Christos-Savvas Bouganis
High-level linear projection circuit design optimization framework for FPGAs under over-clocking. FPL 2012: 723-726
2000 – 2009
- 2009
- [c2]Rui Policarpo Duarte, Horácio C. Neto
Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. DSD 2009: 273-280 - 2008
- [c1]Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias
Multiplier-based double precision floating point divider according to the IEEE-754 standard. ARC 2008: 260-265
Coauthor Index
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