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52nd MICRO 2019: Columbus, OH, USA
- Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019. ACM 2019, ISBN 978-1-4503-6938-1
Accelerators for Machine Learning
- Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin
, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon:
Wire-Aware Architecture and Dataflow for CNN Accelerators. 1-13 - Yakun Sophia Shao, Jason Clemons
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. 14-27 - Alberto Delmas Lascorz, Sayeh Sharify, Isak Edo Vivancos, Dylan Malone Stuart, Omar Mohamed Awad, Patrick Judd, Mostafa Mahmoud, Milos Nikolic, Kevin Siu, Zissis Poulos, Andreas Moshovos:
ShapeShifter: Enabling Fine-Grain Data Width Adaptation in Deep Learning. 28-41
Security 1
- Thomas Bourgeat
MI6: Secure Enclaves in a Speculative Out-of-Order Processor. 42-56 - Austin Harris
Cyclone: Detecting Contention-Based Cache Information Leaks Through Cyclic Interference. 57-72 - Gururaj Saileshwar, Moinuddin K. Qureshi:
CleanupSpec: An "Undo" Approach to Safe Speculation. 73-86
In/Near Memory Computing 1
- Elaheh Sadredini
eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing. 87-99 - Fei Gao, Georgios Tziantzioulis, David Wentzlaff:
ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs. 100-113 - Teyuh Chou, Wei Tang, Jacob Botimer, Zhengya Zhang
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. 114-125
Accelerators for Machine Learning 2
- Berkin Akin, Zeshan A. Chishti, Alaa R. Alameldeen:
ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions. 126-138 - Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. 139-150 - Ashish Gondimalla
SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks. 151-165 - Skanda Koppula, Lois Orosa
EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM. 166-181 - Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang, Li-De Chen:
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference. 182-195
Storage Systems
- Yu-Ching Hu
Dynamic Multi-Resolution Data Storage. 196-210 - Youngseop Shim, Myungsuk Kim, Myoungjun Chun, Jisung Park
Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs. 211-223 - Vikram Sharma Mailthody
DeepStore: In-Storage Acceleration for Intelligent Queries. 224-238 - Mohammadamin Ajdari, Wonsik Lee, Pyeongsu Park, Joonsung Kim, Jangwoo Kim:
FIDR: A Scalable Storage System for Fine-Grain Inline Data Reduction with Efficient Memory Handling. 239-252
Quantum Computing
- Swamit S. Tannu
Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes. 253-265 - Pranav Gokhale, Yongshan Ding
Partial Compilation of Variational Algorithms for Noisy Intermediate-Scale Quantum Machines. 266-278 - Swamit S. Tannu
Mitigating Measurement Errors in Quantum Computers by Exploiting State-Dependent Bias. 279-290 - Poulami Das, Swamit S. Tannu
A Case for Multi-Programming Quantum Computers. 291-303
Accelerators for Emerging Applications
- Eunjin Baek, Hunjun Lee, Youngsok Kim
FlexLearn: Fast and Highly Efficient Brain Simulations Using Flexible On-Chip Learning. 304-318 - Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher:
ExTensor: An Accelerator for Sparse Tensor Algebra. 319-333 - Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin
GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. 334-346 - Fazle Sadi, Joe Sweeney, Tze Meng Low
Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization. 347-358
GPGPUs & Heterogeneous Architectures
- Maohua Zhu, Tao Zhang, Zhenyu Gu, Yuan Xie:
Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs. 359-371 - Oreste Villa, Mark Stephenson, David W. Nellans, Stephen W. Keckler:
NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs. 372-383 - Raghavendra Pradyumna Pothukuchi
Tangram: Integrated Control of Heterogeneous Computers. 384-398 - Jongouk Choi, Qingrui Liu, Changhee Jung:
CoSpec: Compiler Directed Speculative Intermittent Computation. 399-412
Caching
- Zhan Shi, Xiangru Huang, Akanksha Jain, Calvin Lin:
Applying Deep Learning to the Cache Replacement Problem. 413-425 - Ziqiang Huang, José A. Joao, Alejandro Rico, Andrew D. Hilton, Benjamin C. Lee:
DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management. 426-439 - Guowei Zhang, Daniel Sánchez:
Leveraging Caches to Accelerate Hash Tables and Memoization. 440-452 - Seokin Hong, Bülent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair:
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads. 453-465
Emerging Memory & Storage Technology
- Siddharth Gupta
Distributed Logless Atomic Durability with Persistent Memory. 466-478 - Pengfei Zuo, Yu Hua, Yuan Xie:
SuperMem: Enabling Application-transparent Secure Persistent Memory with Low Overheads. 479-492 - Congming Gao, Min Ye, Qiao Li
Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory. 493-505
Microarchitecture
- Hideki Ando:
SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue. 506-518 - Niranjan Soundararajan, Saurabh Gupta, Ragavendra Natarajan, Jared Stark, Rahul Pal, Franck Sala, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney
Towards the adoption of Local Branch Predictors in Modern Out-of-Order Superscalar Processors. 519-530 - Rahul Bera
DSPatch: Dual Spatial Pattern Prefetcher. 531-544
Security 2
- Hongyan Xia, Jonathan Woodruff
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. 545-557 - Hiroshi Sasaki, Miguel A. Arroyo, M. Tarek Ibn Ziad
Practical Byte-Granular Memory Blacklisting using Califorms. 558-571 - Ofir Weisse, Ian Neal, Kevin Loughlin, Thomas F. Wenisch, Baris Kasikci:
NDA: Preventing Speculative Execution Attacks at Their Source. 572-586
Domain Specific Accelerators
- Wenqin Huangfu, Xueqi Li, Shuangchen Li, Xing Hu, Peng Gu, Yuan Xie:
MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm. 587-599 - Konstantinos Kanellopoulos, Nandita Vijaykumar, Christina Giannoula, Roknoddin Azizi, Skanda Koppula, Nika Mansouri-Ghiasi, Taha Shahroodi, Juan Gómez-Luna, Onur Mutlu:
SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations. 600-614 - Mingyu Yan, Xing Hu, Shuangchen Li, Abanti Basak, Han Li, Xin Ma, Itir Akgun, Yujing Feng, Peng Gu, Lei Deng
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach. 615-628 - Tiancheng Xu
Tigris: Architecture and Algorithms for 3D Perception in Point Clouds. 629-642
Mobile and Embedded Architectures
- Yu Feng
ASV: Accelerated Stereo Vision System. 643-656 - Haibo Zhang, Shulin Zhao, Ashutosh Pattnaik, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita R. Das:
Distilling the Essence of Raw Video to Reduce Memory Usage and Energy at Edge Devices. 657-669 - Graham Gobieski, Amolak Nagi, Nathan Serafin, Mehmet Meric Isgenc, Nathan Beckmann, Brandon Lucia:
MANIC: A Vector-Dataflow Architecture for Ultra-Low-Power Embedded Systems. 670-684 - Bryan Donyanavard, Tiago Mück, Amir M. Rahmani
SOSA: Self-Optimizing Learning with Self-Adaptive Control for Hierarchical System-on-Chip Management. 685-698
In/Near Memory Computing 2
- Mohammad Alian
NetDIMM: Low-Latency Near-Memory Network Interface Architecture. 699-711 - Youwei Zhuo, Chao Wang, Mingxing Zhang, Rui Wang, Dimin Niu, Yanzhi Wang, Xuehai Qian:
GraphQ: Scalable PIM-Based Graph Processing. 712-725 - Jaeyoung Jang, Jun Heo, Yejin Lee, Jaeyeon Won, Seonghak Kim, Sungjun Jung, Hakbeom Jang, Tae Jun Ham, Jae W. Lee:
Charon: Specialized Near-Memory Processing Architecture for Clearing Dead Objects in Memory. 726-739 - Youngeun Kwon
TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learning. 740-753
Accelerators for Machine Learning 3
- Hyoukjun Kwon
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. 754-768 - Lillian Pentecost
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation. 769-781 - Franyell Silfa, Gem Dot, José-María Arnau, Antonio González:
Neuron-Level Fuzzy Memoization in RNNs. 782-793 - Jacob R. Stevens, Ashish Ranjan
Manna: An Accelerator for Memory-Augmented Neural Networks. 794-806
Memory Systems & Storage
- Xiao Liu, David Roberts, Rachata Ausavarungnirun, Onur Mutlu, Jishen Zhao:
Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability. 807-820 - Gagandeep Panwar
Quantifying Memory Underutilization in HPC Systems and Using it to Improve Performance via Architecture Support. 821-835 - Yuanjiang Ni, Jishen Zhao, Heiner Litz, Daniel Bittman, Ethan L. Miller:
SSP: Eliminating Redundant Writes in Failure-Atomic NVRAMs via Shadow Sub-Paging. 836-848 - Renhai Chen, Zili Shao, Duo Liu, Zhiyong Feng, Tao Li:
Towards Efficient NVDIMM-based Heterogeneous Storage Hierarchy Management for Big Data Workloads. 849-860
Multicore/Parallel Architectures
- Lucas Morais, Vitor Silva, Alfredo Goldman, Carlos Álvarez
Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor. 861-872 - Mayank Parasar, Natalie D. Enright Jerger, Paul V. Gratz
SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution. 873-885 - Diyu Zhou, Yuval Tamir:
PUSh: Data Race Detection Based on Hardware-Supported Prevention of Unintended Sharing. 886-898 - Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau:
EMI Architectural Model and Core Hopping. 899-910
Reconfigurable Architectures and FPGA
- Zhaoshi Li, Leibo Liu
FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. 911-923 - Vidushi Dadu, Jian Weng, Sihao Liu
Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms. 924-939 - Amirali Sharifian, Reza Hojabr, Navid Rahimi, Sihao Liu
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. 940-953
Security 3
- Jiyong Yu
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data. 954-968 - Daniel Townley, Khaled N. Khasawneh, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
LATCH: A Locality-Aware Taint CHecker. 969-982 - Nader Sehatbakhsh
EMMA: Hardware/Software Attestation Framework for Embedded Systems Using Electromagnetic Signals. 983-995
Caching & Virtualization
- Hao Wu, Krishnendra Nathella, Joseph Pusdesris, Dam Sunwoo, Akanksha Jain, Calvin Lin:
Temporal Prefetching Without the Off-Chip Metadata. 996-1008 - Anurag Mukkara, Nathan Beckmann, Daniel Sánchez:
PHI: Architectural Support for Synchronization- and Bandwidth-Efficient Commutative Scatter Updates. 1009-1022 - Artemiy Margaritov
Prefetched Address Translation. 1023-1036
Measurement, Modeling, and Simulation
- Nikos Nikoleris, Lieven Eeckhout, Erik Hagersten, Trevor E. Carlson:
Directed Statistical Warming through Time Traveling. 1037-1049 - Donggyu Kim, Jerry Zhao, Jonathan Bachrach, Krste Asanovic:
Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection. 1050-1062 - Mohammad Shahrad
Architectural Implications of Function-as-a-Service Computing. 1063-1075
Corrigendum
- Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, Josep Torrellas:
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum). 1076
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