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Thomas Bourgeat

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2020 – today

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2024
[j4]
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Mengjia Yan, Thomas Bourgeat, Sharad Malik:
Formal Verification for Secure Processors: A Guide for Computer Architects. Computer 57(10): 138-143 (2024)
[c16]
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  - conf/itp/GruetterBC24
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Samuel Gruetter, Thomas Bourgeat, Adam Chlipala:
Verifying Software Emulation of an Unsupported Hardware Instruction. ITP 2024: 17:1-17:16
[c15]
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Jiacheng Ma, Rishabh R. Iyer, Sahand Kashani, Mahyar Emami, Thomas Bourgeat, George Candea:
Performance Interfaces for Hardware Accelerators. OSDI 2024: 855-874
[i6]
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  - journals/corr/abs-2403-04714
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Mahyar Emami, Thomas Bourgeat, James R. Larus:
Parendi: Thousand-Way Parallel RTL Simulation. CoRR abs/2403.04714 (2024)
[i5]
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  - journals/corr/abs-2407-12232
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Qinhan Tan, Yuheng Yang, Thomas Bourgeat, Sharad Malik, Mengjia Yan:
RTL Verification for Secure Speculation Using Contract Shadow Logic. CoRR abs/2407.12232 (2024)
2023
[b1]
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  - phd/us/Bourgeat23
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Thomas Bourgeat:
Specification and verification of sequential machines in rule-based hardware languages. MIT, USA, 2023
[j3]
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Thomas Bourgeat, Ian Clester, Andres Erbsen, Samuel Gruetter, Pratap Singh, Andy Wright, Adam Chlipala:
Flexible Instruction-Set Semantics via Abstract Monads (Experience Report). Proc. ACM Program. Lang. 7(ICFP): 108-124 (2023)
[c14]
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  - conf/isca/DeutschNBE023
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Peter W. Deutsch, Weon Taek Na, Thomas Bourgeat, Joel S. Emer, Mengjia Yan:
Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes. ISCA 2023: 38:1-38:16
[c13]
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Yuheng Yang, Thomas Bourgeat, Stella Lau, Mengjia Yan:
Pensieve: Microarchitectural Modeling for Security Evaluation. ISCA 2023: 59:1-59:15
[c12]
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Sabrina M. Neuman, Radhika Ghosal, Thomas Bourgeat, Brian Plancher, Vijay Janapa Reddi:
RoboShape: Using Topology Patterns to Scalably and Flexibly Deploy Accelerators Across Robots. ISCA 2023: 69:1-69:13
[i4]
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  - journals/corr/abs-2306-14882
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Jules Drean, Miguel Gomez-Garcia, Thomas Bourgeat, Srinivas Devadas:
Citadel: Side-Channel-Resistant Enclaves with Secure Shared Memory on a Speculative Out-of-Order Processor. CoRR abs/2306.14882 (2023)
2022
[c11]
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Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel S. Emer, Mengjia Yan:
DAGguise: mitigating memory timing side channels. ASPLOS 2022: 329-343
2021
[j2]
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  - journals/ral/PlancherNBKDR21
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Brian Plancher, Sabrina M. Neuman, Thomas Bourgeat, Scott Kuindersma, Srinivas Devadas, Vijay Janapa Reddi:
Accelerating Robot Dynamics Gradients on a CPU, GPU, and FPGA. IEEE Robotics Autom. Lett. 6(2): 2335-2342 (2021)
[c10]
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Sabrina M. Neuman, Brian Plancher, Thomas Bourgeat, Thierry Tambe, Srinivas Devadas, Vijay Janapa Reddi:
Robomorphic computing: a design methodology for domain-specific accelerators parameterized by robot morphology. ASPLOS 2021: 674-686
[c9]
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  - conf/asplos/Pit-ClaudelBLAC21
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Clément Pit-Claudel, Thomas Bourgeat, Stella Lau, Arvind, Adam Chlipala:
Effective simulation and debugging for a high-level hardware language using software compilers. ASPLOS 2021: 789-803
[c8]
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  - conf/isca/ChenHXBCA21
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Xuhao Chen, Tianhao Huang, Shuotao Xu, Thomas Bourgeat, Chanwoo Chung, Arvind:
FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining. ISCA 2021: 581-594
[i3]
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  - journals/corr/abs-2104-00762
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Thomas Bourgeat, Ian Clester, Andres Erbsen, Samuel Gruetter, Andrew Wright, Adam Chlipala:
A Multipurpose Formal RISC-V Specification. CoRR abs/2104.00762 (2021)
2020
[c7]
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  - conf/micro/XuBHKLA20
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Shuotao Xu, Thomas Bourgeat, Tianhao Huang, Hojun Kim, Sungjin Lee, Arvind:
AQUOMAN: An Analytic-Query Offloading Machine. MICRO 2020: 386-399
[c6]
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  - conf/micro/BourgeatDYTEY20
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Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan:
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches. MICRO 2020: 1110-1123
[c5]
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  - conf/pldi/BourgeatPCA20
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Thomas Bourgeat, Clément Pit-Claudel, Adam Chlipala, Arvind:
The essence of Bluespec: a core language for rule-based hardware design. PLDI 2020: 243-257

2010 – 2019

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2019
[j1]
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Sizhuo Zhang, Andrew Wright, Thomas Bourgeat:
Composable Building Blocks to Open Up Processor Design. IEEE Micro 39(3): 47-55 (2019)
[c4]
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  - conf/micro/BourgeatLWZAD19
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Thomas Bourgeat, Ilia A. Lebedev, Andrew Wright, Sizhuo Zhang, Arvind, Srinivas Devadas:
MI6: Secure Enclaves in a Speculative Out-of-Order Processor. MICRO 2019: 42-56
2018
[c3]
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  - conf/micro/ZhangWBA18
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Sizhuo Zhang, Andrew Wright, Thomas Bourgeat, Arvind:
Composable Building Blocks to Open up Processor Design. MICRO 2018: 68-81
[i2]
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  - journals/corr/abs-1812-09822
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Thomas Bourgeat, Ilia A. Lebedev, Andrew Wright, Sizhuo Zhang, Arvind, Srinivas Devadas:
MI6: Secure Enclaves in a Speculative Out-of-Order Processor. CoRR abs/1812.09822 (2018)
2016
[c2]
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  - conf/async/PedroBC16
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Javier de San Pedro, Thomas Bourgeat, Jordi Cortadella:
Specification Mining for Asynchronous Controllers. ASYNC 2016: 107-114
2014
[c1]
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  - conf/sec/BourgeatBCCCFHMNV14
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Thomas Bourgeat, Julien Bringer, Hervé Chabanne, Robin Champenois, Jérémie Clément, Houda Ferradi, Marc Heinrich, Paul Melotti, David Naccache, Antoine Voizard:
New Algorithmic Approaches to Point Constellation Recognition. SEC 2014: 80-90
[i1]
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Thomas Bourgeat, Julien Bringer, Hervé Chabanne, Robin Champenois, Jérémie Clément, Houda Ferradi, Marc Heinrich, Paul Melotti, David Naccache, Antoine Voizard:
New Algorithmic Approaches to Point Constellation Recognition. CoRR abs/1405.1402 (2014)

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