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EMI Architectural Model and Core Hopping

Authors:

Daphne I. Gorman,

Rafael Trapani Possignolo,

Jose RenauAuthors Info & Claims

MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

Pages 899 - 910

https://doi.org/10.1145/3352460.3358289

Published: 12 October 2019 Publication History

Abstract

Processors radiate electromagnetic interference (EMI), which affects wireless communication technologies. However, despite the fact that the EMI generated by a processor is deterministic, architecturally modeling the EMI has proven to be a complex challenge. Moreover, EMI depends on the physical layout of the processor and on the binary being executed (both the application and its compilation options).

This paper proposes Model for EMI on a SoC (MESC), the first architectural framework for modeling electromagnetic emissions from a core. MESC takes into account the layout and the switching activity of a process to model the expected EMI. We validate MESC on a real system to verify its accuracy. We then use MESC to demonstrate that two different core layouts can be leveraged to reduce EMI and propose EMI Core Hopper (EMI CHopper). EMI CHopper uses a multi-core system -- where each core has the same RTL but minimally different layouts -- and proposes hopping the application between cores to reduce in-band EMI when it interferes with wireless communication.

Our evaluation shows that MESC is able to predict EMI within 95% accuracy across time and across the frequency spectrum, even when using statistical sampling to obtain activity rates. Leveraging MESC, our proposed EMI CHopper reduces in-band EMI by up to 50%, with low impact on performance. MESC will enable a new stream of micro-architectural research the same way architectural level power models have enabled exploration of performance and power simulation.

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Cited By

Sehatbakhsh NYilmaz BZajic APrvulovic M(2020)EMSim: A Microarchitecture-Level Simulation Tool for Modeling Electromagnetic Side-Channel Signals2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00016(71-85)Online publication date: Feb-2020
https://doi.org/10.1109/HPCA47549.2020.00016

Index Terms

EMI Architectural Model and Core Hopping
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multicore architectures
2. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
    2. Simulation evaluation

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cover image ACM Conferences

MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

October 2019

1104 pages

ISBN:9781450369381

DOI:10.1145/3352460

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 12 October 2019

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National Science Foundation

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MICRO '52

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SIGMICRO

MICRO '52: The 52nd Annual IEEE/ACM International Symposium on Microarchitecture

October 12 - 16, 2019

OH, Columbus, USA

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Cited By

Sehatbakhsh NYilmaz BZajic APrvulovic M(2020)EMSim: A Microarchitecture-Level Simulation Tool for Modeling Electromagnetic Side-Channel Signals2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00016(71-85)Online publication date: Feb-2020
https://doi.org/10.1109/HPCA47549.2020.00016

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