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50th MICRO 2017: Cambridge, MA, USA
- Hillery C. Hunter, Jaime Moreno, Joel S. Emer, Daniel Sánchez:
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017. ACM 2017, ISBN 978-1-4503-4952-9
DRAM
- Xiangyao Yu, Christopher J. Hughes
, Nadathur Satish, Onur Mutlu, Srinivas Devadas:
Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation. 1-14 - Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-Hyoun Kim
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. 15-26 - Samira Manabi Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu:
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content. 27-40 - Mike O'Connor
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. 41-54
Accelerators
- Yuanwei Fang, Chen Zou, Aaron J. Elmore
UDP: a programmable accelerator for extract-transform-load workloads and more. 55-68 - Reza Yazdani, José-María Arnau, Antonio González:
UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST composition. 69-81 - Mostafa Mahmoud, Bojian Zheng, Alberto Delmas Lascorz, Felix Heide, Jonathan Assouline, Paul Boucher, Emmanuel Onzon, Andreas Moshovos:
IDEAL: image denoising accelerator. 82-95 - Thomas J. Repetti, João Pedro Cerqueira, Martha A. Kim
Pipelining a triggered processing element. 96-108
GPU-I
- Ivan Tanasic, Isaac Gelado, Marc Jordà, Eduard Ayguadé, Nacho Navarro:
Efficient exception handling support for GPUs. 109-122 - Ugljesa Milic, Oreste Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer Jaleel, Alex Ramírez, David W. Nellans:
Beyond the socket: NUMA-aware GPUs. 123-135 - Rachata Ausavarungnirun, Joshua Landgraf, Vance Miller, Saugata Ghose, Jayneel Gandhi
Mosaic: a GPU memory manager with application-transparent support for multiple page sizes. 136-150 - John Kloosterman
Regless: just-in-time operand staging for GPUs. 151-164 - Pedro Duarte, Pedro Tomás
SCRATCH: an end-to-end application-aware soft-GPGPU architecture and trimming tool. 165-177
Non-volatile memory/storage
- Seunghee Shin, Satish Kumar Tirukkovalluri, James Tuck, Yan Solihin:
Proteus: a flexible and fast software supported hardware logging approach for NVM. 178-190 - Guoyang Chen, Lei Zhang, Richa Budhiraja, Xipeng Shen
Efficient support of position independence on non-volatile memory. 191-203 - Kaisheng Ma
Incidental computing on IoT nonvolatile processors. 204-218 - Gunjae Koo
Summarizer: trading communication with computing near storage. 219-231 - Zhaoxia Deng, Lunkai Zhang, Nikita Mishra, Henry Hoffmann, Frederic T. Chong
Memory cocktail therapy: a general learning-based framework to optimize dynamic tradeoffs in NVMs. 232-244
In/near memory computing
- Sandeep R. Agrawal, Sam Idicula, Arun Raghavan, Evangelos Vlachos, Venkatraman Govindaraju, Venkatanathan Varadarajan, Cagri Balkesen, Georgios Giannikis, Charlie Roth, Nipun Agarwal, Eric Sedlar:
A many-core architecture for in-memory data processing. 245-258 - Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das
Cache automaton. 259-272 - Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie S. Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry:
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology. 273-287 - Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie:
DRISA: a DRAM-based reconfigurable in-situ accelerator. 288-301 - Dimitrios Skarlatos, Nam Sung Kim, Josep Torrellas:
Pageforge: a near-memory content-aware page-merging architecture. 302-314
Security
- Khaled N. Khasawneh, Nael B. Abu-Ghazaleh
RHMD: evasion-resilient hardware malware detectors. 315-327 - Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Software-based gate-level information flow security for IoT systems. 328-340 - Zecheng He, Ruby B. Lee:
How secure is your cache against side-channel attacks? 341-353 - Hoda Naghibijouybari
Constructing and characterizing covert channels on GPGPUs. 354-366
Deep learning
- Jongse Park, Hardik Sharma
Scale-out acceleration for machine learning. 367-381 - Jorge Albericio, Alberto Delmas, Patrick Judd, Sayeh Sharify, Gerard O'Leary, Roman Genov, Andreas Moshovos:
Bit-pragmatic deep neural network computing. 382-394 - Caiwen Ding
CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices. 395-408
Prediction
- Abhishek Bhattacharjee
Using branch predictors to predict brain activity in brain-machine implants. 409-422 - Rami Sheikh, Harold W. Cain, Raguram Damodaran:
Load value prediction via path-based address prediction: avoiding mispredictions due to conflicting stores. 423-435 - Daniel A. Jiménez
Multiperspective reuse prediction. 436-448
Coherence/consistency, translation and virtual memory
- Yashwant Marathe, Nagendra Gulur, Jee Ho Ryoo, Shuang Song, Lizy K. John:
CSALT: context switch aware large TLB. 449-462 - Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer:
RTLcheck: verifying the memory consistency of RTL designs. 463-476 - Opeoluwa Matthews, Daniel J. Sorin:
Architecting hierarchical coherence protocols for push-button parametric verification. 477-489 - Yuanfeng Peng, Benjamin P. Wood, Joseph Devietti:
PARSNIP: performant architecture for race safety with no impact on precision. 490-502
Energy
- George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Peter Lawthers, Shidhartha Das:
Harnessing voltage margins for energy efficiency in multicore CPUs. 503-516 - Haibo Zhang, Prasanna Venkatesh Rengasamy, Shulin Zhao, Nachiappan Chidambaram Nachiappan, Anand Sivasubramaniam, Mahmut T. Kandemir, Ravi R. Iyer, Chita R. Das:
Race-to-sleep + content caching + display caching: a recipe for energy-efficient video streaming on handhelds. 517-531 - Ang Li, Wenfeng Zhao, Shuaiwen Leon Song:
BVF: enabling significant on-chip power savings via bit-value-favor for throughput processors. 532-545 - Aditya Agrawal, Josep Torrellas, Sachin Idgunji:
Xylem: enhancing vertical thermal conduction in 3D processor-memory stacks. 546-559
GPU-II
- Ya-Shuai Lü, Libo Huang, Li Shen, Zhiying Wang:
Unleashing the power of GPU for physically-based rendering via dynamic ray shuffling. 560-573 - Youngsok Kim
GPUpd: a fast and scalable multi-GPU architecture using cooperative projection and distribution. 574-586 - Zhen Zheng, Chanyoung Oh, Jidong Zhai, Xipeng Shen
Versapipe: a versatile programming framework for pipelined computing on GPU. 587-599 - AmirAli Abdolrashidi, Devashree Tripathy
Wireframe: supporting data-dependent parallelism through dependency graph execution in GPUs. 600-611
OS and system design
- Prathmesh Kallurkar, Smruti R. Sarangi:
Schedtask: a hardware-assisted task scheduler. 612-624 - Md. Enamul Haque, Yuxiong He, Sameh Elnikety, Thu D. Nguyen, Ricardo Bianchini, Kathryn S. McKinley:
Exploiting heterogeneity for tail latency and energy efficiency. 625-638 - Christian DeLozier
TMI: thread memory isolation for false sharing repair. 639-650 - Weilong Cui, Timothy Sherwood
Estimating and understanding architectural risk. 651-664
Unconventional architectures
- Yipeng Huang
Hybrid analog-digital solution of nonlinear partial differential equations. 665-678 - Swamit S. Tannu
Taming the instruction bandwidth of quantum computers via hardware-managed error correction. 679-691 - Ali JavadiAbhari, Pranav Gokhale, Adam Holmes, Diana Franklin
Optimized surface code communication in superconducting quantum computers. 692-705 - Ting-Jung Chang, Zhuozhi Yao, Paul J. Jackson, Barry P. Rand
Architectural tradeoffs for biodegradable computing. 706-717
Compilers and microarchitecture
- Joonmoo Huh, James Tuck:
Improving the effectiveness of searching for isomorphic chains in superword level parallelism. 718-729 - Xulong Tang
Data movement aware computation partitioning. 730-744 - Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
Mirage cores: the illusion of many out-of-order cores using in-order hardware. 745-758 - Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten:
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs. 759-773
Best paper nominees
- Daphne I. Gorman, Matthew R. Guthaus, Jose Renau:
Architectural opportunities for novel dynamic EMI shifting (DEMIS). 774-785 - Parker Hill, Animesh Jain, Mason Hill, Babak Zamirai, Chang-Hong Hsu, Michael A. Laurenzano, Scott A. Mahlke, Lingjia Tang, Jason Mars:
DeftNN: addressing bottlenecks for DNN execution on GPUs via synapse vector elimination and near-compute data fission. 786-799 - Tiancong Wang, Sakthikumaran Sambasivam, Yan Solihin, James Tuck:
Hardware supported persistent object address translation. 800-812 - Xiang Fu, Michiel Adriaan Rol
An experimental microarchitecture for a superconducting quantum processor. 813-825
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